Ultra-Low-Latency and Flexible In-memory Key-Value Store System Design on CPU-FPGA. - Yunhui Qiu; Hankun Lv; Jinyu Xie; Wenbo Yin; Lingli Wang (FPT, 2018)

A Low-Latency Multi-Version Key-Value Store Using B-Tree on an FPGA-CPU Platform. - Yuchen Ren; Zhijian Liao; Xiaozhong Shi; Jinyu Xie; Yunhui Qiu; Hankun Lv; Wenbo Yin; Lingli Wang; Bowei Yu; Hua Chen; Xianjun He (FPL, 2019)

High Throughput and Low Latency Multi-Version Management Key-Value Storage Accelerator. - Hankun Lv; Yuchen Ren; Yunhui Qiu; Wenbo Yin; Lingli Wang (FPT, 2020)

FULL-KV: Flexible and Ultra-Low-Latency In-Memory Key-Value Store System Design on CPU-FPGA. - Yunhui Qiu; Jinyu Xie; Hankun Lv; Wenbo Yin; Wai-Shing Luk; Lingli Wang; Bowei Yu; Hua Chen; Xianjun Ge; Zhijian Liao; Xiaozhong Shi (IEEE Trans. Parallel Distributed Syst., 2020)

A 32×32 SPAD LiDAR Sensor with In-pixel Spatial-temporal Coincidence and Per-SPAD Pulse Delay for Resolution-lossless Imaging. - Bu Chen; Zhangcheng Huang 001; Jingyi Wang; Hongyang Shang; Hankun Lv; Qi Liu 010; Ming Liu 022 (A-SSCC, 2024)

A 32×32 Flash LiDAR SPAD Sensor with Up-to-1kfps Motional Target Detection by Threshold-adaptive 2D Dynamic Vision. - Jingyi Wang; Zhangcheng Huang 001; Bu Chen; Hongyang Shang; Jiapei Zheng; Hankun Lv; Chixiao Chen; Qi Liu 010; Ming Liu 022 (CICC, 2024)

CEDAR: Computing-in-pixel Edge-aware Detection and Reconstruction Architecture for High-resolution 3D Imaging. - Bu Chen; Zhangcheng Huang 001; Qi Zheng 004; Weiyi Tang; Jingyi Wang; Hankun Lv; Chixiao Chen; Jianlu Wang; Qi Liu 010 (DAC, 2024)