A clock synchronization system with IEEE 1588-2008 adapters over existing Gigabit Ethernet equipment. - Jiho Han; Hankyu Chi; Deog-Kyoon Jeong (ISCAS, 2010)

12.5-Gb/s analog front-end of an optical transceiver in 0.13-μm CMOS. - Dong-Wook Kim; Hankyu Chi; Yu-Sang Chun; Myung-Heon Chin; Gyungock Kim; Deog-Kyoon Jeong (ISCAS, 2013)

A 20-Gb/s 1.27pJ/b low-power optical receiver front-end in 65nm CMOS. - Gyu-Seob Jeong; Hankyu Chi; Kyungock Kim; Deog-Kyoon Jeong (ISCAS, 2014)

A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers. - Joo-Hyung Chae; Gi-Moon Hong; Jihwan Park; Mino Kim; Hyeongjun Ko; Woo-Yeol Shin; Hankyu Chi; Deog-Kyoon Jeong; Suhwan Kim 001 (A-SSCC, 2015)

Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology. - Woo-Rham Bae; Gyu-Seob Jeong; Yoonsoo Kim; Hankyu Chi; Deog-Kyoon Jeong (IEEE Trans. Very Large Scale Integr. Syst., 2016)

29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration. - Sungwoo Kim 001; Han-Gon Ko; Sung-Yong Cho; Jinhyung Lee; Soyeong Shin; Min-Seong Choo; Hankyu Chi; Deog-Kyoon Jeong (ISSCC, 2017)

A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme. - Dongkyun Kim; Minsu Park; Sungchun Jang; Jun-Yong Song; Hankyu Chi; Geunho Choi; Sunmyung Choi; Jaeil Kim; Changhyun Kim; Kyung Whan Kim; Kibong Koo; Seonghwi Song; et al. (ISSCC, 2019)

A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx. - Dongkyun Kim; Kibong Koo; Yongmi Kim; Dong-Uk Lee; Jaejin Lee; Ki Hun Kwon; Byeongchan Choi; Hongjung Kim; Sanghyun Ku; Jong-Sam Kim; Seungwook Oh; Minsu Park; et al. (IEEE J. Solid State Circuits, 2020)

A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration. - Min-Seong Choo; Sungwoo Kim 001; Han-Gon Ko; Sung-Yong Cho; Kwanseo Park; Jinhyung Lee; Soyeong Shin; Hankyu Chi; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2021)

A 28-Gb/s Single-Ended PAM-4 Receiver With T-Coil-Integrated Continuous-Time Linear Equalizer in 40-nm CMOS Technology. - Taeyang Sim; Sun-Ho Yeom; Hyunwoo Im; Youngmin Oh; Hyeongmin Seo; Hyeongjun Ko; Hankyu Chi; Hae-Kang Jung; Jaeduk Han (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

WITCH: WeIghTed Coding Scheme for Crosstalk Reduction in High Bandwidth Memory. - Seoyoon Jang; Sangouk Jeon; Kwanghyun Shin; Dongkwon Lee; Hankyu Chi; Wookjin Shin; Changhyun Pyo; Jaeha Kim; Dongsuk Jeon (ASP-DAC, 2025)

A 3ns Idle-Exit Latency 0.28-28Gb/s/pin Single-Ended NRZ Die-to-Die Interface with Energy-Efficient Receiver and Background Noise Compensation. - Hyun-Seok Choi; Sunki Cho; Sanghee Lee 002; Hyeri Roh; Jeongeun Song; Honggyoo Ahn; Jihee Kim; Minchang Kim; Hankyu Chi; Deog-Kyoon Jeong; Woo-Seok Choi (CICC, 2025)

ML-Based Fast and Accurate Performance Modeling and Prediction for High-Speed Memory Interfaces Across Different Technologies. - Taehoon Kim; Minjeong Kim; Hankyu Chi; Byungjun Kang; Eunji Song; Woo-Seok Choi (DATE, 2025)

22.3 A 42Gb/s Single-Ended Hybrid-DFE PAM-3 Receiver for GDDR7 Memory Interfaces. - Boram Kim; Hankyu Chi; Hyeongjun Ko; Sang-Yeon Byeon; Sungkwon Lee; Changhyun Pyo; Seulgi Kim; Byungjun Kang; Eunji Song; Kwangjin Na; Jin-Youp Cha; Hyesoo Kim; et al. (ISSCC, 2025)