A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking. - Jung-Sik Kim; Chi Sung Oh; Hocheol Lee; Donghyuk Lee; Hyong-Ryol Hwang; Sooman Hwang; Byongwook Na; Joungwook Moon; Jin-Guk Kim; Hanna Park; Jang-Woo Ryu; Kiwon Park; et al. (ISSCC, 2011)

A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking. - Jung-Sik Kim; Chi Sung Oh; Hocheol Lee; Donghyuk Lee; Hyong-Ryol Hwang; Sooman Hwang; Byongwook Na; Joungwook Moon; Jin-Guk Kim; Hanna Park; Jang-Woo Ryu; Kiwon Park; et al. (IEEE J. Solid State Circuits, 2012)

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme. - Chang-Kyo Lee; Yoon-Joo Eom; Jin-Hee Park; Junha Lee; Hye-Ran Kim; Kihan Kim; Young Choi; Ho-Jun Chang; Jonghyuk Kim; Jong-Min Bang; Seungjun Shin; Hanna Park; et al. (ISSCC, 2017)

13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration. - Sung-Yong Cho; Moon-Chul Choi; Jaehyeok Baek; Donggun An; Sanghoon Kim; Daewoong Lee; Seongyeal Yang; Gil-Young Kang; Juseop Park; Kyungho Lee; Hwan-Chul Jung; Gun-hee Cho; et al. (ISSCC, 2024)

A 16-Gb 37-Gb/s GDDR7 DRAM With PAM3-Optimized TRX Equalization and ZQ Calibration. - Sung-Yong Cho; Moon-Chul Choi; Jaehyeok Baek; Donggun An; Sang-Hoon Kim; Daewoong Lee; Seongyeal Yang; Se-Mi Kim; Gil-Young Kang; Juseop Park; Kyung-Ho Lee; Hwan-Chul Jung; et al. (IEEE J. Solid State Circuits, 2025)