Realization of a Programmable Parallel DSP for High Performance Image Processing Applications. - Jens Peter Wittenburg; Willm Hinrichs; Johannes Kneip; Martin Ohmacht; Mladen Berekovic; Hanno Lieske; Helge Kloos; Peter Pirsch (DAC, 1998)

Software MPEG-2 video decoder on a 200-MHz, low-power multimedia microprocessor. - Kouhei Nadehara; Hanno Lieske; Ichiro Kuroda (ICASSP, 1998)

HiPAR-DSP: Ein 1.3 GOPS Multimedia Signalprozessor. - Jens Peter Wittenburg; Willm Hinrichs; Martin Ohmacht; Hanno Lieske; Helge Kloos; Peter Pirsch (ARCS, 1999)

A 1.3-GOPS parallel DSP for high-performance image-processing applications. - Willm Hinrichs; Jens Peter Wittenburg; Hanno Lieske; Helge Kloos; Martin Ohmacht; Peter Pirsch (IEEE J. Solid State Circuits, 2000)

HiPAR-DSP 16, a scalable highly parallel DSP core for system on a chip video- and image processing applications. - Helge Kloos; Jens Peter Wittenburg; Willm Hinrichs; Hanno Lieske; Lars Friebe; C. Klar; Peter Pirsch (ICASSP, 2002)

A multi DSP board for real time SAR processing using the HiPAR-DSP 16. - Christian Simon-Klar; Lars Friebe; Helge Kloos; Hanno Lieske; Willm Hinrichs; Peter Pirsch (IGARSS, 2002)

A compact and flexible multi-DSP system for real-time SAR applications. - Stefan Langemeyer; Helge Kloos; Christian Simon-Klar; Lars Friebe; Willm Hinrichs; Hanno Lieske; Peter Pirsch (IGARSS, 2003)

A low-cost mixed-mode parallel processor architecture for embedded systems. - Shorin Kyo; Takuya Koga; Hanno Lieske; Shouhei Nomoto; Shin'ichiro Okazaki (ICS, 2007)

IMAPCAR2: A dynamic SIMD/MIMD mode switching processor for embedded systems. - Shorin Kyo; Shouhei Nomoto; Takuya Koga; Hanno Lieske; Shin'ichiro Okazaki (Hot Chips Symposium, 2009)

Efficient data transfer operations for a SIMD processor array system. - Hanno Lieske; Shorin Kyo; Shouhei Nomoto; Sunao Torii; Yuki Kobayashi; Yasuyuki Ninomiya; Shin'ichiro Okazaki (ICASSP, 2012)

4.2 A 12nm Autonomous-Driving Processor with 60.4TOPS, 13.8TOPS/W CNN Executed by Task-Separated ASIL D Control. - Katsushige Matsubara; Hanno Lieske; Motoki Kimura; Atsushi Nakamura; Manabu Koike; Kazuaki Terashima; Shun Morikawa; Yoshihiko Hotta; Takahiro Irita; Seiji Mochizuki; Hiroyuki Hamasaki; Tatsuya Kamei (ISSCC, 2021)

A 12-nm Autonomous Driving Processor With 60.4 TOPS, 13.8 TOPS/W CNN Executed by Task-Separated ASIL D Control. - Katsushige Matsubara; Hanno Lieske; Motoki Kimura; Atsushi Nakamura; Manabu Koike; Shun Morikawa; Yoshihiko Hotta; Takahiro Irita; Seiji Mochizuki; Hiroyuki Hamasaki; Tatsuya Kamei (IEEE J. Solid State Circuits, 2022)