Fast Execution Mechanisms of Parallel Inference Engine PIE: PIEpelined Goal Rewriting and Goal Multicasting. - Hanpei Koike; Hidehiko Tanaka (LP, 1986)

Multi-Context Processing and Data Balancing Mechanism of the Parallel Inference Machine PIE64. - Hanpei Koike; Hidehiko Tanaka (FGCS, 1988)

Distributed Garbage Collection for the Parallel Inference Machine PIE64. - Lu Xu; Hanpei Koike; Hidehiko Tanaka (IFIP Congress, 1989)

Distributed Garbage Collection for the Parallel Inference Engine PIE64. - Lu Xu; Hanpei Koike; Hidehiko Tanaka (NACLP, 1989)

A Static Load Partitioning Method based on Execution Profile for Committed Choice Languages. - Yasuo Hidaka; Hanpei Koike; Jun'ichi Tatemura; Hidehiko Tanaka (ISLP, 1991)

HyperDEBU: A Multiwindow Debugger for Parallel Logic Programs. - Jun'ichi Tatemura; Hanpei Koike; Hidehiko Tanaka (Programming Environments for Parallel Computing, 1992)

The Instruction Set Architecture of the Inference Processor UNIRED II. - Kentaro Shimada; Hanpei Koike; Hidehiko Tanaka (Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, 1993)

Multiple Threads in Cyclic Register Windows. - Yasuo Hidaka; Hanpei Koike; Hidehiko Tanaka (ISCA, 1993)

Control and Data Flow Visualization for Parallel Logic Programs on a Multi-window Debugger HyperDEBU. - Jun'ichi Tatemura; Hanpei Koike; Hidehiko Tanaka (PARLE, 1993)

UNIRED II: The High Performance Inference Processor for the Parallel Inference Machine PIE64. - Kentaro Shimada; Hanpei Koike; Hidehiko Tanaka (New Gener. Comput., 1993)

A Fleng Compiler for PIE64. - Hidemoto Nakada; Takuya Araki; Hanpei Koike; Hidehiko Tanaka (IFIP PACT, 1994)

A Performance Debugger for a Parallel Logic Programming Language Fleng. - Jun'ichi Tatemura; Hanpei Koike; Hidehiko Tanaka (Theory and Practice of Parallel Programming, 1994)

Architecture of parallel management kernel for PIE64. - Yasuo Hidaka; Hanpei Koike; Hidehiko Tanaka (Future Gener. Comput. Syst., 1994)

Parallel Execution of Radix Sort Program Using Fine-Grain Communication. - Yuetsu Kodama; Hirofumi Sakane; Hanpei Koike; Mitsuhisa Sato; Shuichi Sakai; Yoshinori Yamaguchi (IEEE PACT, 1997)

Fast Speculative Search Engine on the Highly Parallel Computer EM-X. - Hayato Yamana; Hanpei Koike; Yuetsu Kodama; Hirofumi Sakane; Yoshinori Yamaguchi (SIGIR, 1998)

Preliminary performance analysis of flex power FPGA, a power reconfigurable device with fine granularity. - Takashi Kawanami; Masakazu Hioki; Hiroshi Nagase; Toshiyuki Tsutsumi; Tadashi Nakagawa; Toshihiro Sekigawa; Hanpei Koike (FPGA, 2004)

Preliminary Evaluation of Flex Power FPGA: A Power Reconfigurable Architecture with Fine Granularity. - Takashi Kawanami; Masakazu Hioki; Hiroshi Nagase; Toshiyuki Tsutsumi; Tadashi Nakagawa; Toshihiro Sekigawa; Hanpei Koike (IEICE Trans. Inf. Syst., 2004)

XDXMOS: a novel technique for the double-gate MOSFETs logic circuits - to achieve high drive current and small input capacitance together. - Hanpei Koike; Toshihiro Sekigawa (CICC, 2005)

FPGAs with multidimensional mesh topology. - Yohei Matsumoto; Hanpei Koike; Akira Masaki (FPGA, 2006)

Evaluation of granularity on threshold voltage control in flex power FPGA. - Masakazu Hioki; Takashi Kawanami; Toshiyuki Tsutsumi; Tadashi Nakagawa; Toshihiro Sekigawa; Hanpei Koike (FPT, 2006)

Optimal set of body bias voltages for an FPGA with field-programmable Vth components. - Takashi Kawanami; Masakazu Hioki; Yohei Matsumoto; Toshiyuki Tsutsumi; Tadashi Nakagawa; Toshihiro Sekigawa; Hanpei Koike (FPT, 2006)

Flex-Pass-Gate SRAM Design for Static Noise Margin Enhancement Using FinFET-Based Technology. - Shin-ichi O'Uchi; Meishoku Masahara; Kunihiro Sakamoto; Kazuhiko Endo; Yongxun Liu; Takashi Matsukawa; Toshihiro Sekigawa; Hanpei Koike; Eiichi Suzuki (CICC, 2007)

Performance and yield enhancement of FPGAs with within-die variation using multiple configurations. - Yohei Matsumoto; Masakazu Hioki; Takashi Kawanami; Toshiyuki Tsutsumi; Tadashi Nakagawa; Toshihiro Sekigawa; Hanpei Koike (FPGA, 2007)

A Power Configurable Block Array Connected in Series as First Prototype Flex Power FPGA Chip. - Masakazu Hioki; Takashi Kawanami; Yohei Matsumoto; Tadashi Nakagawa; Toshihiro Sekigawa; Hanpei Koike; Toshiyuki Tsutsumi (FPT, 2007)

Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA. - Takashi Kawanami; Masakazu Hioki; Yohei Matsumoto; Toshiyuki Tsutsumi; Tadashi Nakagawa; Toshihiro Sekigawa; Hanpei Koike (IEICE Trans. Inf. Syst., 2007)

FinFET-Based Flex-Vth SRAM Design for Drastic Standby-Leakage-Current Reduction. - Shin-ichi O'Uchi; Meishoku Masahara; Kazuhiko Endo; Yongxun Liu; Takashi Matsukawa; Kunihiro Sakamoto; Toshihiro Sekigawa; Hanpei Koike; Eiichi Suzuki (IEICE Trans. Electron., 2008)

Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations. - Yohei Matsumoto; Masakazu Hioki; Takashi Kawanami; Hanpei Koike; Toshiyuki Tsutsumi; Tadashi Nakagawa; Toshihiro Sekigawa (ACM Trans. Reconfigurable Technol. Syst., 2008)

High-speed low-power FinFET based domino logic. - Seid Hadi Rasouli; Hanpei Koike; Kaustav Banerjee (ASP-DAC, 2009)

Development of a CAD tool for 3D-FPGAs. - Naoto Miyamoto; Yohei Matsumoto; Hanpei Koike; Tadayuki Matsumura; Kenichi Osada; Yaoko Nakagawa; Tadahiro Ohmi (3DIC, 2010)

Realization of 0.7-V analog circuits by adaptive-Vt operation of FinFET. - Shin-ichi O'Uchi; Kazuhiko Endo; Yongxun Liu; Tadashi Nakagawa; Takashi Matsukawa; Yuki Ishikawa; Junichi Tsukada; Toshihiro Sekigawa; Hanpei Koike; Kunihiro Sakamoto; Meishoku Masahara (CICC, 2010)

0.5V FinFET SRAM with dynamic threshold control of pass gates for salvaging malfunctioned bits. - Shin-ichi O'Uchi; Kazuhiko Endo; Yongxun Liu; Tadashi Nakagawa; Takashi Matsukawa; Yuki Ishikawa; Junichi Tsukada; Hiromi Yamauchi; Toshihiro Sekigawa; Hanpei Koike; Kunihiro Sakamoto; Meishoku Masahara (ESSCIRC, 2010)

A 0.7-V Opamp in Scaled Low-Standby-Power FinFET Technology. - Shin-ichi O'Uchi; Kazuhiko Endo; Takashi Matsukawa; Yongxun Liu; Tadashi Nakagawa; Yuki Ishikawa; Junichi Tsukada; Hiromi Yamauchi; Toshihiro Sekigawa; Hanpei Koike; Kunihiro Sakamoto; Meishoku Masahara (IEICE Trans. Electron., 2012)

High-Frequency Precise Characterization of Intrinsic FinFET Channel. - Hideo Sakai; Shin-ichi O'Uchi; Takashi Matsukawa; Kazuhiko Endo; Yongxun Liu; Junichi Tsukada; Yuki Ishikawa; Tadashi Nakagawa; Toshihiro Sekigawa; Hanpei Koike; Kunihiro Sakamoto; Meishoku Masahara; et al. (IEICE Trans. Electron., 2012)

Fully-functional FPGA prototype with fine-grain programmable body biasing. - Masakazu Hioki; Toshihiro Sekigawa; Tadashi Nakagawa; Hanpei Koike; Yohei Matsumoto; Takashi Kawanami; Toshiyuki Tsutsumi (FPGA, 2013)

Standard cell implementation of buskeeper PUF with symmetric inverters and neighboring cells for passing randomness tests. - Yasuhiro Ogasahara; Yohei Hori; Hanpei Koike (GCCE, 2015)

Impacts of flexible Vth control, low process variability, and steep SS with low on-current of new structure transistors to ultra-low voltage designs. - Yasuhiro Ogasahara; Tadashi Nakagawa; Toshihiro Sekigawa; Toshiyuki Tsutsumi; Hanpei Koike (IEICE Electron. Express, 2015)

Implementation of pseudo linear feedback shift register physical unclonable function on silicon. - Yasuhiro Ogasahara; Yohei Hori; Hanpei Koike (ISCAS, 2016)

Low Overhead Design of Power Reconfigurable FPGA with Fine-Grained Body Biasing on 65-nm SOTB CMOS Technology. - Masakazu Hioki; Hanpei Koike (IEICE Trans. Inf. Syst., 2016)

Development of an Evaluation Platform and Performance Experimentation of Flex Power FPGA Device. - Toshihiro Katashita; Masakazu Hioki; Yohei Hori; Hanpei Koike (IEICE Trans. Inf. Syst., 2018)

Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge-Response pair acquisition using Built-In Self-Test before shipping. - Yasuhiro Ogasahara; Yohei Hori; Toshihiro Katashita; Tomoki Iizuka; Hiromitsu Awano; Makoto Ikeda; Hanpei Koike (Integr., 2020)

A Cryogenic CMOS Current Comparator for Spin Qubit Readout Achieving Fast Readout Time and High Current Resolution. - Hiroshi Fuketa; Ippei Akita; Tomohiro Ishikawa; Hanpei Koike; Takahiro Mori (VLSI Technology and Circuits, 2022)

A Cryogenic CMOS Current Integrator and Correlation Double Sampling Circuit for Spin Qubit Readout. - Hiroshi Fuketa; Ippei Akita; Tomohiro Ishikawa; Hanpei Koike; Takahiro Mori (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)