FPGA implementation of template matching using binary sum of absolute difference. - Aditya Rachman Putra; Fadhil Mochammad; Hans Herdian (ICSET, 2016)

Ultra-Low-Power Atomic Clock for Satellite Constellation with 2.2×10-12 Long-Term Allan Deviation Using Cesium Coherent Population Trapping. - Haosheng Zhang; Hans Herdian; Aravind Tharayil Narayanan; Atsushi Shirane; Mitsuru Suzuki; Kazuhiro Harasaka; Kazuhiko Adachi; Shinya Yanagimachi; Kenichi Okada 001 (ISSCC, 2019)

0.2mW 70Fsrms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur. - Haosheng Zhang; Aravind Tharayil Narayanan; Hans Herdian; Bangan Liu; Yun Wang 008; Atsushi Shirane; Kenichi Okada 001 (VLSI Circuits, 2019)

A Power-Efficient Pulse-VCO for Chip-Scale Atomic Clock. - Haosheng Zhang; Aravind Tharayil Narayanan; Hans Herdian; Bangan Liu; Rui Wu 001; Atsushi Shirane; Kenichi Okada 001 (IEICE Trans. Electron., 2019)

ULPAC: A Miniaturized Ultralow-Power Atomic Clock. - Haosheng Zhang; Hans Herdian; Aravind Tharayil Narayanan; Atsushi Shirane; Mitsuru Suzuki; Kazuhiro Harasaka; Kazuhiko Adachi; Shigeyoshi Goka; Shinya Yanagimachi; Kenichi Okada 001 (IEEE J. Solid State Circuits, 2019)

Dual-Layer Proton Irradiation for Creating Thermally-Stable High-Resistivity Region in Si CMOS Substrate. - Hans Herdian; Takeshi Inoue; Takuichi Hirano; Masatsugu Sogabe; Atsushi Shirane; Kenichi Okada 001 (ESSDERC, 2021)

32.7 A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth. - Junjun Qiu; Zheng Sun 001; Bangan Liu; Wenqian Wang; Dingxin Xu; Hans Herdian; Hongye Huang; Yuncheng Zhang; Yun Wang 008; Atsushi Shirane; Kenichi Okada 001 (ISSCC, 2021)

A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth. - Junjun Qiu; Zheng Sun 001; Bangan Liu; Wenqian Wang; Dingxin Xu; Hans Herdian; Hongye Huang; Yuncheng Zhang; Yun Wang 008; Jian Pang; Hanli Liu; Masaya Miyahara; et al. (IEEE J. Solid State Circuits, 2021)

A Small-Satellite-Mounted 256-Element Ka-Band CMOS Phased-Array Transmitter Achieving 63.8dBm EIRP Under 26.6W Power Consumption Using Single/Dual Circular Polarization Active Coupler. - Dongwon You; Xi Fu; Xiaolin Wang; Yuan Gao; Wenqian Wang; Jun Sakamaki; Hans Herdian; Sena Kato; Michihiro Ide; Yuncheng Zhang; Ashbir Aviat Fadila; Zheng Li 021; et al. (ISSCC, 2023)

A Sub-THz Full-Duplex Phased-Array Transceiver with Self-Interference Cancellation and LO Feedthrough Suppression. - Chun Wang; Ibrahim Abdo; Chenxin Liu; Carrel da Gomez; Hans Herdian; Wenqian Wang; Xi Fu; Dongwon You; Abanob Shehata; Sunghwan Park; Yun Wang 008; Jian Pang; et al. (VLSI Technology and Circuits, 2023)

A Ka-Band Deployable Active Phased Array Transmitter Fabricated on 4-Layer Liquid Crystal Polymer Substrate for Small-Satellite Mount. - Dongwon You; Xiaolin Wang; Hans Herdian; Xi Fu; Hojun Lee; Michihiro Ide; Carrel da Gomez; Zheng Li 021; Jill C. Mayeda; Daisuke Awaji; Jian Pang; Hiraku Sakamoto; et al. (IEEE Access, 2023)

35-60GHz Switchless IF Bi-Directional Amplifier Using 65nm CMOS for 300GHz-Band Transceivers. - Abanob Shehata; Hans Herdian; Chun Wang; Chenxin Liu; Kazuaki Kunihiro; Hiroyuki Sakai 009; Atsushi Shirane; Kenichi Okada 001 (A-SSCC, 2024)

24.3 A 236-to-266GHz 4-Element Amplifier-Last Phased-Array Transmitter in 65nm CMOS. - Chun Wang; Hans Herdian; Wenbin Zheng; Chenxin Liu; Jill C. Mayeda; Yuxuan Liu; Olivia Angel Yong; Wenqian Wang; Yuncheng Zhang; Carrel da Gomez; Abanob Shehata; Sena Kato; et al. (ISSCC, 2024)

A 640-Gb/s 4×4-MIMO D-Band CMOS Transceiver Chipset. - Chenxin Liu; Zheng Li 021; Yudai Yamazaki; Hans Herdian; Chun Wang; Anyi Tian; Jun Sakamaki; Han Nie; Xi Fu; Sena Kato; Wenqian Wang; Hongye Huang; et al. (VLSI Technology and Circuits, 2024)

A Sub-THz Full-Duplex Phased-Array Transceiver With Self-Interference Cancellation and LO Feedthrough Suppression. - Chun Wang; Ibrahim Abdo; Chenxin Liu; Carrel da Gomez; Jill C. Mayeda; Hans Herdian; Wenqian Wang; Xi Fu; Dongwon You; Abanob Shehata; Sunghwan Park; Yun Wang 008; et al. (IEEE J. Solid State Circuits, 2024)

A D-Band CMOS Transceiver Chipset Supporting 640Gb/s Date Rate with 4?4 Line-of-Sight MIMO. - Chenxin Liu; Zheng Li 021; Yudai Yamazaki; Hans Herdian; Chun Wang; Anyi Tian; Jun Sakamaki; Han Nie; Xi Fu; Sena Kato; Wenqian Wang; Hongye Huang; et al. (ASP-DAC, 2025)

A 640-Gb/s 4 × 4-MIMO D-Band CMOS Transceiver Chipset. - Chenxin Liu; Zheng Li 021; Yudai Yamazaki; Hans Herdian; Chun Wang; Anyi Tian; Jun Sakamaki; Han Nie; Xi Fu; Sena Kato; Wenqian Wang; Hongye Huang; et al. (IEEE J. Solid State Circuits, 2025)