PROTEST: a tool for probabilistic testability analysis. - Hans-Joachim Wunderlich (DAC, 1985)

On fault modeling for dynamic MOS circuits. - Hans-Joachim Wunderlich; Wolfgang Rosenstiel (DAC, 1986)

Probabilistische Verfahren für den Test hochintegrierter Schaltungen - Hans-Joachim Wunderlich (Springer, 1987)

On Computing Optimized Input Probabilities for Random Tests. - Hans-Joachim Wunderlich (DAC, 1987)

Generating pattern sequences for the pseudo-exhaustive test of MOS-circuits. - Hans-Joachim Wunderlich; Sybille Hellebrand (FTCS, 1988)

Automatisierung des Entwurfs vollständig testbarer Schaltungen. - Sybille Hellebrand; Hans-Joachim Wunderlich (GI Jahrestagung (2), 1988)

The design of random-testable sequential circuits. - Hans-Joachim Wunderlich (FTCS, 1989)

The Pseudo-Exhaustive Test of Sequential Circuits. - Sybille Hellebrand; Hans-Joachim Wunderlich (ITC, 1989)

Tools and devices supporting the pseudo-exhaustive test. - Sybille Hellebrand; Hans-Joachim Wunderlich (EURO-DAC, 1990)

The effectiveness of different test sets for PLAs. - Peter C. Maxwell; Hans-Joachim Wunderlich (EURO-DAC, 1990)

Optimized synthesis of self-testable finite state machines. - Bernhard Eschermann; Hans-Joachim Wunderlich (FTCS, 1990)

Generating pseudo-exhaustive vectors for external testing. - Sybille Hellebrand; Hans-Joachim Wunderlich; Oliver F. Haberl (ITC, 1990)

Error masking in self-testable circuits. - Albrecht P. Stroele; Hans-Joachim Wunderlich (ITC, 1990)

An analytical approach to the partial scan problem. - Arno Kunzmann; Hans-Joachim Wunderlich (J. Electron. Test., 1990)

Multiple distributions for biased random test patterns. - Hans-Joachim Wunderlich (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

A Unified Approach for the Synthesis of Self-Testable Finite State Machines. - Bernhard Eschermann; Hans-Joachim Wunderlich (DAC, 1991)

Signature Analysis and Test Scheduling for Self-Testable Circuits. - Albrecht P. Stroele; Hans-Joachim Wunderlich (FTCS, 1991)

Emulation of Scan Paths in Sequential Circuit Synthesis. - Bernhard Eschermann; Hans-Joachim Wunderlich (Fault-Tolerant Computing Systems, 1991)

A Common Approach to Test Generation and Hardware Verification Based on Temporal Logic. - Thomas Kropf; Hans-Joachim Wunderlich (ITC, 1991)

TESTCHIP: a chip for weighted random pattern generation, evaluation, and test control. - Albrecht P. Ströle; Hans-Joachim Wunderlich (IEEE J. Solid State Circuits, 1991)

Prüfgerechter Entwurf und Test hochintegrierter Schaltungen. - Hans-Joachim Wunderlich; Michael H. Schulz (Inform. Spektrum, 1992)

Optimized synthesis techniques for testable sequential circuits. - Bernhard Eschermann; Hans-Joachim Wunderlich (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

The pseudoexhaustive test of sequential circuits. - Hans-Joachim Wunderlich; Sybille Hellebrand (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Synthesis of Self-Testable Controllers. - Sybille Hellebrand; Hans-Joachim Wunderlich (EDAC-ETC-EUROASIC, 1994)

An efficient procedure for the synthesis of fast self-testable controller structures. - Sybille Hellebrand; Hans-Joachim Wunderlich (ICCAD, 1994)

Simulation Results of an Efficient Defect-Analysis Procedure. - Olaf Stern; Hans-Joachim Wunderlich (ITC, 1994)

Configuring Flip-Flops to BIST Registers. - Albrecht P. Stroele; Hans-Joachim Wunderlich (ITC, 1994)

Synthesis of IDDQ-testable circuits: integrating built-in current sensors. - Hans-Joachim Wunderlich; M. Herzog; Joan Figueras; Juan A. Carrasco; Angel Calderón (ED&TC, 1995)

Pattern generation for a deterministic BIST scheme. - Sybille Hellebrand; Birgit Reeb; Steffen Tarnick; Hans-Joachim Wunderlich (ICCAD, 1995)

Test register insertion with minimum hardware cost. - Albrecht P. Stroele; Hans-Joachim Wunderlich (ICCAD, 1995)

Deterministic Pattern Generation for Weighted Random Pattern Testing. - Birgit Reeb; Hans-Joachim Wunderlich (ED&TC, 1996)

Bit-flipping BIST. - Hans-Joachim Wunderlich; Gundolf Kiefer (ICCAD, 1996)

Fast controllers for data dominated applications. - Andre Hertwig; Hans-Joachim Wunderlich (ED&TC, 1997)

Using BIST Control for Pattern Generation. - Gundolf Kiefer; Hans-Joachim Wunderlich (ITC, 1997)

Power Dissipation During Testing: Should We Worry About it? - Vishwani D. Agrawal; Robert C. Aitken; J. Braden; Joan Figueras; S. Kumar; Hans-Joachim Wunderlich; Yervant Zorian (VTS, 1997)

Guest Editorial. - Kwang-Ting Cheng; Kewal K. Saluja; Hans-Joachim Wunderlich (J. Electron. Test., 1997)

Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST. - Madhavi Karkala; Nur A. Touba; Hans-Joachim Wunderlich (Asian Test Symposium, 1998)

Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs. - Vyacheslav N. Yarmolik; Sybille Hellebrand; Hans-Joachim Wunderlich (DATE, 1998)

Accumulator based deterministic BIST. - Rainer Dorsch; Hans-Joachim Wunderlich (ITC, 1998)

Fast Self-Recovering Controllers. - Andre Hertwig; Sybille Hellebrand; Hans-Joachim Wunderlich (VTS, 1998)

Synthesizing Fast, Online-Testable Control Units. - Sybille Hellebrand; Hans-Joachim Wunderlich; Andre Hertwig (IEEE Des. Test Comput., 1998)

Mixed-Mode BIST Using Embedded Processors. - Sybille Hellebrand; Hans-Joachim Wunderlich; Andre Hertwig (J. Electron. Test., 1998)

BIST for systems-on-a-chip. - Hans-Joachim Wunderlich (Integr., 1998)

Hardware-optimal test register insertion. - Albrecht P. Stroele; Hans-Joachim Wunderlich (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Symmetric Transparent BIST for RAMs. - Sybille Hellebrand; Hans-Joachim Wunderlich; Vyacheslav N. Yarmolik (DATE, 1999)

Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms. - Vyacheslav N. Yarmolik; I. V. Bykov; Sybille Hellebrand; Hans-Joachim Wunderlich (EDCC, 1999)

Error Detecting Refreshment for Embedded DRAMs. - Sybille Hellebrand; Hans-Joachim Wunderlich; Alexander A. Ivaniuk; Yuri V. Klimets; Vyacheslav N. Yarmolik (VTS, 1999)

Deterministic BIST with Multiple Scan Chains. - Gundolf Kiefer; Hans-Joachim Wunderlich (J. Electron. Test., 1999)

Optimal Hardware Pattern Generation for Functional BIST. - Silvia Cataldo; Silvia Chiusano; Paolo Prinetto; Hans-Joachim Wunderlich (DATE, 2000)

Non-intrusive BIST for systems-on-a-chip. - Silvia Chiusano; Paolo Prinetto; Hans-Joachim Wunderlich (ITC, 2000)

Minimized Power Consumption for Scan-Based BIST. - Stefan Gerstendörfer; Hans-Joachim Wunderlich (J. Electron. Test., 2000)

Deterministic BIST with Partial Scan. - Gundolf Kiefer; Hans-Joachim Wunderlich (J. Electron. Test., 2000)

On applying the set covering model to reseeding. - Silvia Chiusano; Stefano Di Carlo; Paolo Prinetto; Hans-Joachim Wunderlich (DATE, 2001)

Using mission logic for embedded testing. - Rainer Dorsch; Hans-Joachim Wunderlich (DATE, 2001)

Circuit partitioning for efficient logic BIST synthesis. - Alexander Irion; Gundolf Kiefer; Harald P. E. Vranken; Hans-Joachim Wunderlich (DATE, 2001)

Tailoring ATPG for embedded testing. - Rainer Dorsch; Hans-Joachim Wunderlich (ITC, 2001)

Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability. - Michael Kessler; Gundolf Kiefer; Jens Leenstra; Knut Schünemann; Thomas Schwarz; Hans-Joachim Wunderlich (ITC, 2001)

A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. - Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch; Hans-Joachim Wunderlich (VTS, 2001)

A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters. - Sybille Hellebrand; Huaguo Liang; Hans-Joachim Wunderlich (J. Electron. Test., 2001)

Application of Deterministic Logic BIST on Industrial Circuits. - Gundolf Kiefer; Harald P. E. Vranken; Erik Jan Marinissen; Hans-Joachim Wunderlich (J. Electron. Test., 2001)

RESPIN++ - deterministic embedded test. - Lars Schäfer; Rainer Dorsch; Hans-Joachim Wunderlich (ETW, 2002)

Combining deterministic logic BIST with test point insertion. - Harald P. E. Vranken; Florian Meister; Hans-Joachim Wunderlich (ETW, 2002)

Adapting an SoC to ATE Concurrent Test Capabilities. - Rainer Dorsch; Ramón Huerta Rivera; Hans-Joachim Wunderlich; Martin Fischer (ITC, 2002)

High Defect Coverage with Low-Power Test Sequences in a BIST Environment. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel; Hans-Joachim Wunderlich (IEEE Des. Test Comput., 2002)

Reusing Scan Chains for Test Pattern Decompression. - Rainer Dorsch; Hans-Joachim Wunderlich (J. Electron. Test., 2002)

Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST. - Huaguo Liang; Sybille Hellebrand; Hans-Joachim Wunderlich (J. Electron. Test., 2002)

A Mixed-Mode BIST Scheme Based on Folding Compression. - Huaguo Liang; Sybille Hellebrand; Hans-Joachim Wunderlich (J. Comput. Sci. Technol., 2002)

Efficient Online and Offline Testing of Embedded DRAMs. - Sybille Hellebrand; Hans-Joachim Wunderlich; Alexander A. Ivaniuk; Yuri V. Klimets; Vyacheslav N. Yarmolik (IEEE Trans. Computers, 2002)

Test Engineering Education in Europe: the EuNICE-Test Project. - Yves Bertrand; Marie-Lise Flottes; Luz Balado; Joan Figueras; Anton Biasizzo; Franc Novak; Stefano Di Carlo; Paolo Prinetto; Nicoleta Pricopi; Hans-Joachim Wunderlich; Jean-Pierre Van der Heyden (MSE, 2003)

Introduction. - Shishpal Rawat; Hans-Joachim Wunderlich (ACM Trans. Design Autom. Electr. Syst., 2003)

Reliability Considerations forMechatronic Systems on the Basis of a State Model. - Talal Arnaout; Peter Göhner; Hans-Joachim Wunderlich; Eduard Zimmer (ARCS Workshops, 2004)

Impact of Test Point Insertion on Silicon Area and Timing during Layout. - Harald P. E. Vranken; Ferry Syafei Sapei; Hans-Joachim Wunderlich (DATE, 2004)

Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ. - Marie-Lise Flottes; Yves Bertrand; Luz Balado; Emili Lupon; Anton Biasizzo; Franc Novak; Stefano Di Carlo; Paolo Prinetto; Nicoleta Pricopi; Hans-Joachim Wunderlich (DELTA, 2004)

Efficient Pattern Mapping for Deterministic Logic BIST. - Valentin Gherman; Hans-Joachim Wunderlich; Harald P. E. Vranken; Friedrich Hapke; Michael Wittke; Michael Garbers (ITC, 2004)

X-Masking During Logic BIST and Its Impact on Defect Coverage. - Yuyi Tang; Hans-Joachim Wunderlich; Harald P. E. Vranken; Friedrich Hapke; Michael Wittke; Piet Engelke; Ilia Polian; Bernd Becker 001 (ITC, 2004)

Panel Summaries. - Hans-Joachim Wunderlich; Sandeep K. Shukla (IEEE Des. Test Comput., 2004)

From embedded test to embedded diagnosis. - Hans-Joachim Wunderlich (ETS, 2005)

On the Reliability Evaluation of SRAM-Based FPGA Designs. - Olivier Héron; Talal Arnaout; Hans-Joachim Wunderlich (FPL, 2005)

Software-basierender Selbsttest von Prozessorkernen unter Verlustleistungsbeschränkung. - Jun Zhou 009; Hans-Joachim Wunderlich (GI Jahrestagung (1), 2005)

Development of an audio player as system-on-a-chip using an open source platform. - Pattara Kiatisevi; Luis Leonardo Azuara-Gomez; Rainer Dorsch; Hans-Joachim Wunderlich (ISCAS (3), 2005)

Implementing a Scheme for External Deterministic Self-Test. - Abdul Wahid Hakmi; Hans-Joachim Wunderlich; Valentin Gherman; Michael Garbers; Jürgen Schlöffel (VTS, 2005)

Software-based self-test of processors under power constraints. - Jun Zhou 009; Hans-Joachim Wunderlich (DATE, 2006)

Some Common Aspects of Design Validation, Debug and Diagnosis. - Talal Arnaout; Gunter Bartsch; Hans-Joachim Wunderlich (DELTA, 2006)

BIST Power Reduction Using Scan-Chain Disable in the Cell Processor. - Christian G. Zoellin; Hans-Joachim Wunderlich; Nicolas Mäding; Jens Leenstra (ITC, 2006)

Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing. - Nabil Badereddine; Patrick Girard 001; Serge Pravossoudovitch; Christian Landrault; Arnaud Virazel; Hans-Joachim Wunderlich (VLSI-SoC, 2006)

DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems). - Bernd Becker 001; Ilia Polian; Sybille Hellebrand; Bernd Straube; Hans-Joachim Wunderlich (it Inf. Technol., 2006)

X-masking during logic BIST and its impact on defect coverage. - Yuyi Tang; Hans-Joachim Wunderlich; Piet Engelke; Ilia Polian; Bernd Becker 001; Jürgen Schlöffel; Friedrich Hapke; Michael Wittke (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Scan Test Planning for Power Reduction. - Michael E. Imhof; Christian G. Zoellin; Hans-Joachim Wunderlich; Nicolas Mäding; Jens Leenstra (DAC, 2007)

Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. - Philipp Öhler; Sybille Hellebrand; Hans-Joachim Wunderlich (DDECS, 2007)

A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. - Sybille Hellebrand; Christian G. Zoellin; Hans-Joachim Wunderlich; Stefan Ludwig; Torsten Coym; Bernd Straube (DFT, 2007)

An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy. - Philipp Öhler; Sybille Hellebrand; Hans-Joachim Wunderlich (ETS, 2007)

Synthesis of irregular combinational functions with large don't care sets. - Valentin Gherman; Hans-Joachim Wunderlich; R. D. Mascarenhas; Jürgen Schlöffel; Michael Garbers (ACM Great Lakes Symposium on VLSI, 2007)

Programmable deterministic Built-In Self-Test. - Abdul Wahid Hakmi; Hans-Joachim Wunderlich; Christian G. Zoellin; Andreas Glowatz; Friedrich Hapke; Jürgen Schlöffel; Laurent Souef (ITC, 2007)

Deterministic logic BIST for transition fault testing. - Valentin Gherman; Hans-Joachim Wunderlich; Jürgen Schlöffel; Michael Garbers (IET Comput. Digit. Tech., 2007)

Scan chain clustering for test power reduction. - Melanie Elm; Hans-Joachim Wunderlich; Michael E. Imhof; Christian G. Zoellin; Jens Leenstra; Nicolas Mäding (DAC, 2008)

Scan Chain Organization for Embedded Diagnosis. - Melanie Elm; Hans-Joachim Wunderlich (DATE, 2008)

Test Set Stripping Limiting the Maximum Number of Specified Bits. - Michael A. Kochte; Christian G. Zoellin; Michael E. Imhof; Hans-Joachim Wunderlich (DELTA, 2008)

Selective Hardening in Early Design Steps. - Christian G. Zoellin; Hans-Joachim Wunderlich; Ilia Polian; Bernd Becker 001 (ETS, 2008)

Integrating Scan Design and Soft Error Correction in Low-Power Applications. - Michael E. Imhof; Hans-Joachim Wunderlich; Christian G. Zoellin (IOLTS, 2008)

Signature Rollback - A Technique for Testing Robust Circuits. - Uranmandakh Amgalan; Christian Hachmann; Sybille Hellebrand; Hans-Joachim Wunderlich (VTS, 2008)

A diagnosis algorithm for extreme space compaction. - Stefan Holst; Hans-Joachim Wunderlich (DATE, 2009)

Test exploration and validation using transaction level models. - Michael A. Kochte; Christian G. Zoellin; Michael E. Imhof; Rauf Salimi Khaligh; Martin Radetzki; Hans-Joachim Wunderlich; Stefano Di Carlo; Paolo Prinetto (DATE, 2009)

Software-Based Hardware Fault Tolerance for Many-Core Architectures. - Hans-Joachim Wunderlich (DFT, 2009)

Test Encoding for Extreme Response Compaction. - Michael A. Kochte; Stefan Holst; Melanie Elm; Hans-Joachim Wunderlich (ETS, 2009)

Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead. - Michael A. Kochte; Christian G. Zoellin; Hans-Joachim Wunderlich (ETS, 2009)

Restrict Encoding for Mixed-Mode BIST. - Abdul Wahid Hakmi; Stefan Holst; Hans-Joachim Wunderlich; Jürgen Schlöffel; Friedrich Hapke; Andreas Glowatz (VTS, 2009)

Adaptive Debug and Diagnosis Without Fault Dictionaries. - Stefan Holst; Hans-Joachim Wunderlich (J. Electron. Test., 2009)

On Determining the Real Output Xs by SAT-Based Reasoning. - Melanie Elm; Michael A. Kochte; Hans-Joachim Wunderlich (Asian Test Symposium, 2010)

Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level. - Michael A. Kochte; Christian G. Zoellin; Rafal Baranowski; Michael E. Imhof; Hans-Joachim Wunderlich; Nadereh Hatami; Stefano Di Carlo; Paolo Prinetto (Asian Test Symposium, 2010)

Efficient fault simulation on many-core processors. - Michael A. Kochte; Marcel Schaal; Hans-Joachim Wunderlich; Christian G. Zoellin (DAC, 2010)

BISD: Scan-based Built-In self-diagnosis. - Melanie Elm; Hans-Joachim Wunderlich (DATE, 2010)

Massive statistical process variations: A grand challenge for testing nanoelectronic circuits. - Bernd Becker 001; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren; Hans-Joachim Wunderlich (DSN Workshops, 2010)

Algorithm-based fault tolerance for many-core architectures. - Claus Braun; Hans-Joachim Wunderlich (ETS, 2010)

System reliability evaluation using concurrent multi-level simulation of structural faults. - Michael A. Kochte; Christian G. Zoellin; Rafal Baranowski; Michael E. Imhof; Hans-Joachim Wunderlich; Nadereh Hatami; Stefano Di Carlo; Paolo Prinetto (ITC, 2010)

Parity prediction synthesis for nano-electronic gate designs. - D. A. Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Hans-Joachim Wunderlich (ITC, 2010)

Low-power test planning for arbitrary at-speed delay-test clock schemes. - Christian G. Zoellin; Hans-Joachim Wunderlich (VTS, 2010)

Efficient Concurrent Self-Test with Partially Specified Patterns. - Michael A. Kochte; Christian G. Zoellin; Hans-Joachim Wunderlich (J. Electron. Test., 2010)

Algorithmen-basierte Fehlertoleranz für Many-Core-Architekturen (Algorithm-based Fault-Tolerance on Many-Core Architectures). - Claus Braun; Hans-Joachim Wunderlich (it Inf. Technol., 2010)

Diagnostic Test of Robust Circuits. - Alejandro Cook; Sybille Hellebrand; Thomas Indlekofer; Hans-Joachim Wunderlich (Asian Test Symposium, 2011)

Efficient BDD-based Fault Simulation in Presence of Unknown Values. - Michael A. Kochte; Sandip Kundu; Kohei Miyase; Xiaoqing Wen; Hans-Joachim Wunderlich (Asian Test Symposium, 2011)

Embedded Test for Highly Accurate Defect Localization. - Abdullah Mumtaz; Michael E. Imhof; Stefan Holst; Hans-Joachim Wunderlich (Asian Test Symposium, 2011)

A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. - D. A. Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Hans-Joachim Wunderlich (Asian Test Symposium, 2011)

Design and architectures for dependable embedded systems. - Jörg Henkel; Lars Bauer; Joachim Becker; Oliver Bringmann 001; Uwe Brinkschulte; Samarjit Chakraborty; Michael Engel; Rolf Ernst; Hermann Härtig; Lars Hedrich; Andreas Herkersdorf; Rüdiger Kapitza; et al. (CODES+ISSS, 2011)

SAT-based fault coverage evaluation in the presence of unknown values. - Michael A. Kochte; Hans-Joachim Wunderlich (DATE, 2011)

Structural In-Field Diagnosis for Random Logic Circuits. - Alejandro Cook; Melanie Elm; Hans-Joachim Wunderlich; Ulrich Abelein (ETS, 2011)

Structural Test for Graceful Degradation of NoC Switches. - Atefe Dalirsani; Stefan Holst; Melanie Elm; Hans-Joachim Wunderlich (ETS, 2011)

Towards Variation-Aware Test Methods. - Ilia Polian; Bernd Becker 001; Sybille Hellebrand; Hans-Joachim Wunderlich; Peter C. Maxwell (ETS, 2011)

Fail-safety in core-based system design. - Rafal Baranowski; Hans-Joachim Wunderlich (IOLTS, 2011)

Soft error correction in embedded storage elements. - Michael E. Imhof; Hans-Joachim Wunderlich (IOLTS, 2011)

SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures. - Michael A. Kochte; Kohei Miyase; Xiaoqing Wen; Seiji Kajihara; Yuta Yamato; Kazunari Enokimoto; Hans-Joachim Wunderlich (ISLPED, 2011)

P-PET: Partial pseudo-exhaustive test for high defect coverage. - Abdullah Mumtaz; Michael E. Imhof; Hans-Joachim Wunderlich (ITC, 2011)

Efficient multi-level fault simulation of HW/SW systems for structural faults. - Rafal Baranowski; Stefano Di Carlo; Nadereh Hatami; Michael E. Imhof; Michael A. Kochte; Paolo Prinetto; Hans-Joachim Wunderlich; Christian G. Zoellin (Sci. China Inf. Sci., 2011)

Variation-aware fault modeling. - Fabian Hopsch; Bernd Becker 001; Sybille Hellebrand; Ilia Polian; Bernd Straube; Wolfgang Vermeiren; Hans-Joachim Wunderlich (Sci. China Inf. Sci., 2011)

OTERA: Online test strategies for reliable reconfigurable architectures - Invited paper for the AHS-2012 special session "Dependability by reconfigurable hardware". - Lars Bauer; Claus Braun; Michael E. Imhof; Michael A. Kochte; Hongyan Zhang 004; Hans-Joachim Wunderlich; Jörg Henkel (AHS, 2012)

Reuse of Structural Volume Test Methods for In-System Testing of Automotive ASICs. - Alejandro Cook; Dominik Ull; Melanie Elm; Hans-Joachim Wunderlich; Helmut Randoll; Stefan Dohren (Asian Test Symposium, 2012)

Variation-Aware Fault Grading. - Alexander Czutro; Michael E. Imhof; J. Jiang; Abdullah Mumtaz; Matthias Sauer 002; Bernd Becker 001; Ilia Polian; Hans-Joachim Wunderlich (Asian Test Symposium, 2012)

Scan Test Power Simulation on GPGPUs. - Stefan Holst; Eric Schneider; Hans-Joachim Wunderlich (Asian Test Symposium, 2012)

Parallel simulation of apoptotic receptor-clustering on GPGPU many-core architectures. - Claus Braun; Markus Daub; Alexander Schöll; Guido Schneider; Hans-Joachim Wunderlich (BIBM, 2012)

Built-in self-diagnosis exploiting strong diagnostic windows in mixed-mode test. - Alejandro Cook; Sybille Hellebrand; Hans-Joachim Wunderlich (ETS, 2012)

Efficient system-level aging prediction. - Nadereh Hatami; Rafal Baranowski; Paolo Prinetto; Hans-Joachim Wunderlich (ETS, 2012)

Exact stuck-at fault classification in presence of unknowns. - Stefan Hillebrecht; Michael A. Kochte; Hans-Joachim Wunderlich; Bernd Becker 001 (ETS, 2012)

Acceleration of Monte-Carlo molecular simulations on hybrid computing architectures. - Claus Braun; Stefan Holst; Hans-Joachim Wunderlich; Juan Manuel Castillo-Sanchez; Joachim Gross (ICCD, 2012)

Transparent structural online test for reconfigurable systems. - Mohamed Abdelfattah; Lars Bauer; Claus Braun; Michael E. Imhof; Michael A. Kochte; Hongyan Zhang 004; Jörg Henkel; Hans-Joachim Wunderlich (IOLTS, 2012)

Modeling, verification and pattern generation for reconfigurable scan networks. - Rafal Baranowski; Michael A. Kochte; Hans-Joachim Wunderlich (ITC, 2012)

Built-in self-diagnosis targeting arbitrary defects with partial pseudo-exhaustive test. - Alejandro Cook; Sybille Hellebrand; Michael E. Imhof; Abdullah Mumtaz; Hans-Joachim Wunderlich (LATW, 2012)

A pseudo-dynamic comparator for error detection in fault tolerant architectures. - D. A. Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Aida Todri; Michael E. Imhof; Hans-Joachim Wunderlich (VTS, 2012)

Structural Test and Diagnosis for Graceful Degradation of NoC Switches. - Atefe Dalirsani; Stefan Holst; Melanie Elm; Hans-Joachim Wunderlich (J. Electron. Test., 2012)

Accurate X-Propagation for Test Applications by SAT-Based Reasoning. - Michael A. Kochte; Melanie Elm; Hans-Joachim Wunderlich (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Securing Access to Reconfigurable Scan Networks. - Rafal Baranowski; Michael A. Kochte; Hans-Joachim Wunderlich (Asian Test Symposium, 2013)

Accurate Multi-cycle ATPG in Presence of X-Values. - Dominik Erb; Michael A. Kochte; Matthias Sauer 002; Hans-Joachim Wunderlich; Bernd Becker 001 (Asian Test Symposium, 2013)

Accurate QBF-based test pattern generation in presence of unknown values. - Stefan Hillebrecht; Michael A. Kochte; Dominik Erb; Hans-Joachim Wunderlich; Bernd Becker 001 (DATE, 2013)

Efficient variation-aware statistical dynamic timing analysis for delay test applications. - Marcus Wagner; Hans-Joachim Wunderlich (DATE, 2013)

Synthesis of workload monitors for on-line stress prediction. - Rafal Baranowski; Alejandro Cook; Michael E. Imhof; Chang Liu 010; Hans-Joachim Wunderlich (DFTS, 2013)

SAT-based code synthesis for fault-secure circuits. - Atefe Dalirsani; Michael A. Kochte; Hans-Joachim Wunderlich (DFTS, 2013)

Scan pattern retargeting and merging with reduced access time. - Rafal Baranowski; Michael A. Kochte; Hans-Joachim Wunderlich (ETS, 2013)

Efficacy and efficiency of algorithm-based fault-tolerance on GPUs. - Hans-Joachim Wunderlich; Claus Braun; Sebastian Halder 002 (IOLTS, 2013)

Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures. - Hongyan Zhang 004; Lars Bauer; Michael A. Kochte; Eric Schneider; Claus Braun; Michael E. Imhof; Hans-Joachim Wunderlich; Jörg Henkel (ITC, 2013)

Test Strategies for Reliable Runtime Reconfigurable Architectures. - Lars Bauer; Claus Braun; Michael E. Imhof; Michael A. Kochte; Eric Schneider; Hongyan Zhang 004; Jörg Henkel; Hans-Joachim Wunderlich (IEEE Trans. Computers, 2013)

On Covering Structural Defects in NoCs by Functional Tests. - Atefe Dalirsani; Nadereh Hatami; Michael E. Imhof; Marcus Eggenberger; Gert Schley; Martin Radetzki; Hans-Joachim Wunderlich (ATS, 2014)

High Quality System Level Test and Diagnosis. - Artur Jutman; Matteo Sonza Reorda; Hans-Joachim Wunderlich (ATS, 2014)

Adaptive parallel simulation of a two-timescale model for apoptotic receptor-clustering on GPUs. - Alexander Schöll; Claus Braun; Markus Daub; Guido Schneider; Hans-Joachim Wunderlich (BIBM, 2014)

Advanced Diagnosis: SBST and BIST Integration in Automotive E/E Architectures. - Felix Reimann; Michael Glaß; Jürgen Teich; Alejandro Cook; Laura Rodríguez Gómez; Dominik Ull; Hans-Joachim Wunderlich; Piet Engelke; Ulrich Abelein (DAC, 2014)

GUARD: GUAranteed Reliability in Dynamically Reconfigurable Systems. - Hongyan Zhang 004; Michael A. Kochte; Michael E. Imhof; Lars Bauer; Hans-Joachim Wunderlich; Jörg Henkel (DAC, 2014)

Non-intrusive integration of advanced diagnosis features in automotive E/E-architectures. - Ulrich Abelein; Alejandro Cook; Piet Engelke; Michael Glaß; Felix Reimann; Laura Rodríguez Gómez; Thomas Russ; Jürgen Teich; Dominik Ull; Hans-Joachim Wunderlich (DATE, 2014)

Bit-Flipping Scan - A unified architecture for fault tolerance and offline test. - Michael E. Imhof; Hans-Joachim Wunderlich (DATE, 2014)

A-ABFT: Autonomous Algorithm-Based Fault Tolerance for Matrix Multiplications on Graphics Processing Units. - Claus Braun; Sebastian Halder 002; Hans-Joachim Wunderlich (DSN, 2014)

Diagnosis of multiple faults with highly compacted test responses. - Alejandro Cook; Hans-Joachim Wunderlich (ETS, 2014)

Variation-aware deterministic ATPG. - Matthias Sauer 002; Ilia Polian; Michael E. Imhof; Abdullah Mumtaz; Eric Schneider; Alexander Czutro; Hans-Joachim Wunderlich; Bernd Becker 001 (ETS, 2014)

Incremental computation of delay fault detection probability for variation-aware test generation. - Marcus Wagner; Hans-Joachim Wunderlich (ETS, 2014)

Data-parallel simulation for fast and accurate timing validation of CMOS circuits. - Eric Schneider; Stefan Holst; Xiaoqing Wen; Hans-Joachim Wunderlich (ICCAD, 2014)

Area-efficient synthesis of fault-secure NoC switches. - Atefe Dalirsani; Michael A. Kochte; Hans-Joachim Wunderlich (IOLTS, 2014)

Test pattern generation in presence of unknown values based on restricted symbolic logic. - Dominik Erb; Karsten Scheibler; Michael A. Kochte; Matthias Sauer 002; Hans-Joachim Wunderlich; Bernd Becker 001 (ITC, 2014)

FAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defects. - Sybille Hellebrand; Thomas Indlekofer; Matthias Kampmann; Michael A. Kochte; Chang Liu 010; Hans-Joachim Wunderlich (ITC, 2014)

Verifikation Rekonfigurierbarer Scan-Netze. - Rafal Baranowski; Michael A. Kochte; Hans-Joachim Wunderlich (MBMV, 2014)

Structural Software-Based Self-Test of Network-on-Chip. - Atefe Dalirsani; Michael E. Imhof; Hans-Joachim Wunderlich (VTS, 2014)

Access Port Protection for Reconfigurable Scan Networks. - Rafal Baranowski; Michael A. Kochte; Hans-Joachim Wunderlich (J. Electron. Test., 2014)

Adaptive Bayesian Diagnosis of Intermittent Faults. - Laura Rodríguez Gómez; Alejandro Cook; Thomas Indlekofer; Sybille Hellebrand; Hans-Joachim Wunderlich (J. Electron. Test., 2014)

A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. - D. A. Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Hans-Joachim Wunderlich (J. Electron. Test., 2014)

SAT-based ATPG beyond stuck-at fault testing. - Sybille Hellebrand; Hans-Joachim Wunderlich (it Inf. Technol., 2014)

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience. - Andreas Herkersdorf; Hananeh Aliee; Michael Engel; Michael Glaß; Christina Gimmler-Dumont; Jörg Henkel; Veit Kleeberger; Michael A. Kochte; Johannes Maximilian Kühn; Daniel Mueller-Gritschneder; Sani R. Nassif; Holm Rauchfuss; et al. (Microelectron. Reliab., 2014)

Exact Logic and Fault Simulation in Presence of Unknowns. - Dominik Erb; Michael A. Kochte; Matthias Sauer 002; Stefan Hillebrecht; Tobias Schubert 001; Hans-Joachim Wunderlich; Bernd Becker 001 (ACM Trans. Design Autom. Electr. Syst., 2014)

Multilevel Simulation of Nonfunctional Properties by Piecewise Evaluation. - Nadereh Hatami; Rafal Baranowski; Paolo Prinetto; Hans-Joachim Wunderlich (ACM Trans. Design Autom. Electr. Syst., 2014)

Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch. - Koji Asada; Xiaoqing Wen; Stefan Holst; Kohei Miyase; Seiji Kajihara; Michael A. Kochte; Eric Schneider; Hans-Joachim Wunderlich; Jun Qian (ATS, 2015)

Optimized Selection of Frequencies for Faster-Than-at-Speed Test. - Matthias Kampmann; Michael A. Kochte; Eric Schneider; Thomas Indlekofer; Sybille Hellebrand; Hans-Joachim Wunderlich (ATS, 2015)

Intermittent and Transient Fault Diagnosis on Sparse Code Signatures. - Michael A. Kochte; Atefe Dalirsani; Andrea Bernabei; Martin Omaña 001; Cecilia Metra; Hans-Joachim Wunderlich (ATS, 2015)

On-line prediction of NBTI-induced aging rates. - Rafal Baranowski; Farshad Firouzi; Saman Kiamehr; Chang Liu 010; Mehdi Baradaran Tahoori; Hans-Joachim Wunderlich (DATE, 2015)

GPU-accelerated small delay fault simulation. - Eric Schneider; Stefan Holst; Michael A. Kochte; Xiaoqing Wen; Hans-Joachim Wunderlich (DATE, 2015)

Low-overhead fault-tolerance for the preconditioned conjugate gradient solver. - Alexander Schöll; Claus Braun; Michael A. Kochte; Hans-Joachim Wunderlich (DFTS, 2015)

Testing visions. - Hans-Joachim Wunderlich (ETS, 2015)

STRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable Architectures. - Hongyan Zhang 004; Michael A. Kochte; Eric Schneider; Lars Bauer; Hans-Joachim Wunderlich; Jörg Henkel (ICCAD, 2015)

Efficient observation point selection for aging monitoring. - Chang Liu 010; Michael A. Kochte; Hans-Joachim Wunderlich (IOLTS, 2015)

Efficient on-line fault-tolerance for the preconditioned conjugate gradient method. - Alexander Schöll; Claus Braun; Michael A. Kochte; Hans-Joachim Wunderlich (IOLTS, 2015)

Multi-Layer Test and Diagnosis for Dependable NoCs. - Hans-Joachim Wunderlich; Martin Radetzki (NOCS, 2015)

Adaptive multi-layer techniques for increased system dependability. - Lars Bauer; Jörg Henkel; Andreas Herkersdorf; Michael A. Kochte; Johannes Maximilian Kühn; Wolfgang Rosenstiel; Thomas Schweizer; Stefan Wallentowitz; Volker Wenzel; Thomas Wild; Hans-Joachim Wunderlich; Hongyan Zhang 004 (it Inf. Technol., 2015)

Fine-Grained Access Management in Reconfigurable Scan Networks. - Rafal Baranowski; Michael A. Kochte; Hans-Joachim Wunderlich (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Accurate QBF-Based Test Pattern Generation in Presence of Unknown Values. - Dominik Erb; Michael A. Kochte; Sven Reimer; Matthias Sauer 002; Hans-Joachim Wunderlich; Bernd Becker 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Reconfigurable Scan Networks: Modeling, Verification, and Optimal Pattern Generation. - Rafal Baranowski; Michael A. Kochte; Hans-Joachim Wunderlich (ACM Trans. Design Autom. Electr. Syst., 2015)

High-Throughput Logic Timing Simulation on GPGPUs. - Stefan Holst; Michael E. Imhof; Hans-Joachim Wunderlich (ACM Trans. Design Autom. Electr. Syst., 2015)

Mixed 01X-RSL-Encoding for fast and accurate ATPG with unknowns. - Dominik Erb; Karsten Scheibler; Michael A. Kochte; Matthias Sauer 002; Hans-Joachim Wunderlich; Bernd Becker 001 (ASP-DAC, 2016)

Functional Diagnosis for Graceful Degradation of NoC Switches. - Atefe Dalirsani; Hans-Joachim Wunderlich (ATS, 2016)

A Neural-Network-Based Fault Classifier. - Laura Rodríguez Gómez; Hans-Joachim Wunderlich (ATS, 2016)

Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test. - Stefan Holst; Eric Schneider; Xiaoqing Wen; Seiji Kajihara; Yuta Yamato; Hans-Joachim Wunderlich; Michael A. Kochte (ATS, 2016)

Test Strategies for Reconfigurable Scan Networks. - Michael A. Kochte; Rafal Baranowski; Marcel Schaal; Hans-Joachim Wunderlich (ATS, 2016)

High-Throughput Transistor-Level Fault Simulation on GPUs. - Eric Schneider; Hans-Joachim Wunderlich (ATS, 2016)

Autonomous Testing for 3D-ICs with IEEE Std. 1687. - Jin-Cun Ye; Michael A. Kochte; Kuen-Jong Lee; Hans-Joachim Wunderlich (ATS, 2016)

Applying efficient fault tolerance to enable the preconditioned conjugate gradient solver on approximate computing hardware. - Alexander Schöll; Claus Braun; Hans-Joachim Wunderlich (DFT, 2016)

Efficient Algorithm-Based Fault Tolerance for Sparse Matrix Operations. - Alexander Schöll; Claus Braun; Michael A. Kochte; Hans-Joachim Wunderlich (DSN, 2016)

Formal verification of secure reconfigurable scan network infrastructure. - Michael A. Kochte; Rafal Baranowski; Matthias Sauer 002; Bernd Becker 001; Hans-Joachim Wunderlich (ETS, 2016)

ETS 2015 best paper. - Hans-Joachim Wunderlich; Peter C. Maxwell (ETS, 2016)

Pushing the limits: How fault tolerance extends the scope of approximate computing. - Hans-Joachim Wunderlich; Claus Braun; Alexander Schöll (IOLTS, 2016)

Dependable on-chip infrastructure for dependable MPSOCs. - Michael A. Kochte; Hans-Joachim Wunderlich (LATS, 2016)

Fault tolerance of approximate compute algorithms. - Hans-Joachim Wunderlich; Claus Braun; Alexander Schöll (VTS, 2016)

Structure-Oriented Test of Reconfigurable Scan Networks. - Dominik Ull; Michael A. Kochte; Hans-Joachim Wunderlich (ATS, 2017)

Specification and verification of security in reconfigurable scan networks. - Michael A. Kochte; Matthias Sauer 002; Laura Rodríguez Gómez; Pascal Raiola; Bernd Becker 001; Hans-Joachim Wunderlich (ETS, 2017)

Probabilistic sensitization analysis for variation-aware path delay fault test evaluation. - Marcus Wagner; Hans-Joachim Wunderlich (ETS, 2017)

Energy-efficient and error-resilient iterative solvers for approximate computing. - Alexander Schöll; Claus Braun; Hans-Joachim Wunderlich (IOLTS, 2017)

Trustworthy reconfigurable access to on-chip infrastructure. - Michael A. Kochte; Rafal Baranowski; Hans-Joachim Wunderlich (ITC-Asia, 2017)

Analysis and mitigation or IR-Drop induced scan shift-errors. - Stefan Holst; Eric Schneider; Koshi Kawagoe; Michael A. Kochte; Kohei Miyase; Hans-Joachim Wunderlich; Seiji Kajihara; Xiaoqing Wen (ITC, 2017)

Special session on early life failures. - Jyotirmoy V. Deshmukh; Wolfgang Kunz; Hans-Joachim Wunderlich; Sybille Hellebrand (VTS, 2017)

Aging monitor reuse for small delay fault testing. - Chang Liu 010; Michael A. Kochte; Hans-Joachim Wunderlich (VTS, 2017)

Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip. - Gert Schley; Atefe Dalirsani; Marcus Eggenberger; Nadereh Hatami; Hans-Joachim Wunderlich; Martin Radetzki (IEEE Trans. Computers, 2017)

Aging Resilience and Fault Tolerance in Runtime Reconfigurable Architectures. - Hongyan Zhang 004; Lars Bauer; Michael A. Kochte; Eric Schneider; Hans-Joachim Wunderlich; Jörg Henkel (IEEE Trans. Computers, 2017)

GPU-Accelerated Simulation of Small Delay Faults. - Eric Schneider; Michael A. Kochte; Stefan Holst; Xiaoqing Wen; Hans-Joachim Wunderlich (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Multi-level timing simulation on GPUs. - Eric Schneider; Michael A. Kochte; Hans-Joachim Wunderlich (ASP-DAC, 2018)

Extending Aging Monitors for Early Life and Wear-Out Failure Prevention. - Chang Liu 010; Eric Schneider; Matthias Kampmann; Sybille Hellebrand; Hans-Joachim Wunderlich (ATS, 2018)

Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing. - Yucong Zhang; Xiaoqing Wen; Stefan Holst; Kohei Miyase; Seiji Kajihara; Hans-Joachim Wunderlich; Jun Qian (ATS, 2018)

Online prevention of security violations in reconfigurable scan networks. - Ahmed Atteya; Michael A. Kochte; Matthias Sauer 002; Pascal Raiola; Bernd Becker 001; Hans-Joachim Wunderlich (ETS, 2018)

Device aging: A reliability and security concern. - Daniel Kraak; Mottaqiallah Taouil; Said Hamdioui; Pieter Weckx; Francky Catthoor; Abhijit Chatterjee; Adit D. Singh; Hans-Joachim Wunderlich; Naghmeh Karimi (ETS, 2018)

Detecting and Resolving Security Violations in Reconfigurable Scan Networks. - Pascal Raiola; Michael A. Kochte; Ahmed Atteya; Laura Rodríguez Gómez; Hans-Joachim Wunderlich; Bernd Becker 001; Matthias Sauer 002 (IOLTS, 2018)

Self-Test and Diagnosis for Self-Aware Systems. - Michael A. Kochte; Hans-Joachim Wunderlich (IEEE Des. Test, 2018)

Guest Editor's Introduction. - Hans-Joachim Wunderlich; Yervant Zorian (IEEE Des. Test, 2018)

Guest Editors' Introduction. - Sybille Hellebrand; Jörg Henkel; Anand Raghunathan; Hans-Joachim Wunderlich (IEEE Embed. Syst. Lett., 2018)

On Secure Data Flow in Reconfigurable Scan Networks. - Pascal Raiola; Benjamin Thiemann; Jan Burchard; Ahmed Atteya; Natalia Lylina; Hans-Joachim Wunderlich; Bernd Becker 001; Matthias Sauer 002 (DATE, 2019)

Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses. - Stefan Holst; Eric Schneider; Michael A. Kochte; Xiaoqing Wen; Hans-Joachim Wunderlich (ITC, 2019)

Security Compliance Analysis of Reconfigurable Scan Networks. - Natalia Lylina; Ahmed Atteya; Pascal Raiola; Matthias Sauer 002; Bernd Becker 001; Hans-Joachim Wunderlich (ITC, 2019)

Multi-level timing and fault simulation on GPUs. - Eric Schneider; Hans-Joachim Wunderlich (Integr., 2019)

Built-In Test for Hidden Delay Faults. - Matthias Kampmann; Michael A. Kochte; Chang Liu 010; Eric Schneider; Sybille Hellebrand; Hans-Joachim Wunderlich (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

SWIFT: Switch-Level Fault Simulation on GPUs. - Eric Schneider; Hans-Joachim Wunderlich (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Using Programmable Delay Monitors for Wear-Out and Early Life Failure Prediction. - Chang Liu 010; Eric Schneider; Hans-Joachim Wunderlich (DATE, 2020)

Synthesis of Fault-Tolerant Reconfigurable Scan Networks. - Sebastian Brandhofer; Michael A. Kochte; Hans-Joachim Wunderlich (DATE, 2020)

GPU-accelerated Time Simulation of Systems with Adaptive Voltage and Frequency Scaling. - Eric Schneider; Hans-Joachim Wunderlich (DATE, 2020)

Variation-Aware Defect Characterization at Cell Level. - Zahra Paria Najafi-Haghi; Marzieh Hashemipour-Nazari; Hans-Joachim Wunderlich (ETS, 2020)

Logic Fault Diagnosis of Hidden Delay Defects. - Stefan Holst; Matthias Kampmann; Alexander Sprenger; Jan Dennis Reimer; Sybille Hellebrand; Hans-Joachim Wunderlich; Xiaoqing Wen (ITC, 2020)

Security Preserving Integration and Resynthesis of Reconfigurable Scan Networks. - Natalia Lylina; Ahmed Atteya; Chih-Hao Wang; Hans-Joachim Wunderlich (ITC, 2020)

Switch Level Time Simulation of CMOS Circuits with Adaptive Voltage and Frequency Scaling. - Eric Schneider; Hans-Joachim Wunderlich (VTS, 2020)

Concurrent Test of Reconfigurable Scan Networks for Self-Aware Systems. - Chih-Hao Wang; Natalia Lylina; Ahmed Atteya; Tong-Yu Hsieh; Hans-Joachim Wunderlich (IOLTS, 2021)

Testability-Enhancing Resynthesis of Reconfigurable Scan Networks. - Natalia Lylina; Chih-Hao Wang; Hans-Joachim Wunderlich (ITC, 2021)

Resistive Open Defect Classification of Embedded Cells under Variations. - Zahra Paria Najafi-Haghi; Hans-Joachim Wunderlich (LATS, 2021)

A Hybrid Protection Scheme for Reconfigurable Scan Networks. - Natalia Lylina; Ahmed Atteya; Hans-Joachim Wunderlich (VTS, 2021)

Stress-Aware Periodic Test of Interconnects. - Somayeh Sadeghi Kohan; Sybille Hellebrand; Hans-Joachim Wunderlich (J. Electron. Test., 2021)

Online Periodic Test of Reconfigurable Scan Networks. - Natalia Lylina; Chih-Hao Wang; Hans-Joachim Wunderlich (ATS, 2022)

Intelligent Methods for Test and Reliability. - Hussam Amrouch; Jens Anders; Steffen Becker 001; Maik Betka; Gerd Bleher; Peter Domanski; Nourhan Elhamawy; Thomas Ertl; Athanasios Gatzastras; Paul R. Genssler; Sebastian Hasler; Martin Heinrich; et al. (DATE, 2022)

Robust Reconfigurable Scan Networks. - Natalia Lylina; Chih-Hao Wang; Hans-Joachim Wunderlich (DATE, 2022)

On Extracting Reliability Information from Speed Binning. - Zahra Paria Najafi-Haghi; Florian Klemme; Hussam Amrouch; Hans-Joachim Wunderlich (ETS, 2022)

Efficient and Robust Resistive Open Defect Detection Based on Unsupervised Deep Learning. - Yiwen Liao; Zahra Paria Najafi-Haghi; Hans-Joachim Wunderlich; Bin Yang 009 (ITC, 2022)

SCAR: Security Compliance Analysis and Resynthesis of Reconfigurable Scan Networks. - Natalia Lylina; Chih-Hao Wang; Hans-Joachim Wunderlich (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A Complete Design-for-Test Scheme for Reconfigurable Scan Networks. - Natalia Lylina; Chih-Hao Wang; Hans-Joachim Wunderlich (J. Electron. Test., 2022)

Optimizing the Streaming of Sensor Data with Approximate Communication. - Somayeh Sadeghi Kohan; Jan Dennis Reimer; Sybille Hellebrand; Hans-Joachim Wunderlich (ATS, 2023)

Robust Resistive Open Defect Identification Using Machine Learning with Efficient Feature Selection. - Zahra Paria Najafi-Haghi; Florian Klemme; Hanieh Jafarzadeh; Hussam Amrouch; Hans-Joachim Wunderlich (DATE, 2023)

Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication. - Somayeh Sadeghi Kohan; Sybille Hellebrand; Hans-Joachim Wunderlich (DSN-W, 2023)

Guardband Optimization for the Preconditioned Conjugate Gradient Algorithm. - Natalia Lylina; Stefan Holst; Hanieh Jafarzadeh; Alexandra Kourfali; Hans-Joachim Wunderlich (DSN-W, 2023)

Synthesis of IJTAG Networks for Multi-Power Domain Systems on Chips. - Payam Habiby; Natalia Lylina; Chih-Hao Wang; Hans-Joachim Wunderlich; Sebastian Huhn 001; Rolf Drechsler (ETS, 2023)

Exploiting the Error Resilience of the Preconditioned Conjugate Gradient Method for Energy and Delay Optimization. - Natalia Lylina; Stefan Holst; Hanieh Jafarzadeh; Alexandra Kourfali; Hans-Joachim Wunderlich (IOLTS, 2023)

Robust Pattern Generation for Small Delay Faults Under Process Variations. - Hanieh Jafarzadeh; Florian Klemme; Jan Dennis Reimer; Zahra Paria Najafi-Haghi; Hussam Amrouch; Sybille Hellebrand; Hans-Joachim Wunderlich (ITC, 2023)

Test Aspects of System Health State Monitoring. - Hans-Joachim Wunderlich; Hanieh Jafarzadeh; Alexandra Kourfali; Natalia Lylina; Zahra Paria Najafi-Haghi (LATS, 2023)

Identifying Resistive Open Defects in Embedded Cells under Variations. - Zahra Paria Najafi-Haghi; Hans-Joachim Wunderlich (J. Electron. Test., 2023)

RAPPER: Robust and APProximate ERror Tolerating Communication. - Somayeh Sadeghi Kohan; Sybille Hellebrand; Hans-Joachim Wunderlich (DFT, 2024)

Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations. - Hanieh Jafarzadeh; Florian Klemme; Hussam Amrouch; Sybille Hellebrand; Hans-Joachim Wunderlich (ETS, 2024)

Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing. - Hanieh Jafarzadeh; Florian Klemme; Jan Dennis Reimer; Hussam Amrouch; Sybille Hellebrand; Hans-Joachim Wunderlich (ITC, 2024)

Vmin Testing under Variations: Defect vs. Fault Coverage. - Hanieh Jafarzadeh; Florian Klemme; Hussam Amrouch; Sybille Hellebrand; Hans-Joachim Wunderlich (LATS, 2024)

Workload-Aware Periodic Interconnect BIST. - Somayeh Sadeghi Kohan; Sybille Hellebrand; Hans-Joachim Wunderlich (IEEE Des. Test, 2024)

Robust Pattern Generation for Small Delay Faults under the Impact of Variations. - Hanieh Jafarzadeh; Sybille Hellebrand; Hans-Joachim Wunderlich (ETS, 2025)

European Test Symposium Teams: an Anniversary Snapshot. - Maksim Jenihhin; Jaan Raik; Artur Jutman; Natalia Cherezova; Raimund Ubar; Liviu Miclea; Szilárd Enyedi; I. Stefan; Ovidiu Stan; Cosmina Corches; Z. Peng; Petru Eles; et al. (ETS, 2025)

Robust DLBIST for Delay Fault Testing: Minimizing PVT Variability with Zero Temperature Coefficient (ZTC) Voltage. - Hanieh Jafarzadeh; Florian Klemme; Hussam Amrouch; Sybille Hellebrand; Hans-Joachim Wunderlich (LATS, 2025)

Zero Overhead Error-Tolerant Communication. - Somayeh Sadeghi Kohan; Sybille Hellebrand; Hans-Joachim Wunderlich (LATS, 2025)

Small Delay Fault Testing with Multiple Voltages under Variations: Defect vs. Fault Coverage. - Hanieh Jafarzadeh; Florian Klemme; Hussam Amrouch; Sybille Hellebrand; Hans-Joachim Wunderlich (J. Electron. Test., 2025)