Synthesizing Certificates in Networks of Timed Automata. - Bernd Finkbeiner; Hans-Jörg Peter; Sven Schewe (RTSS, 2008)

RESY: Requirement Synthesis for Compositional Model Checking. - Bernd Finkbeiner; Hans-Jörg Peter; Sven Schewe (TACAS, 2008)

Component-Based Abstraction Refinement for Timed Controller Synthesis. - Hans-Jörg Peter; Robert Mattmüller (RTSS, 2009)

Model Checking the FlexRay Physical Layer Protocol. - Michael Gerke 002; Rüdiger Ehlers; Bernd Finkbeiner; Hans-Jörg Peter (FMICS, 2010)

Combining Symbolic Representations for Solving Timed Games. - Rüdiger Ehlers; Robert Mattmüller; Hans-Jörg Peter (FORMATS, 2010)

Making the Right Cut in Model Checking Data-Intensive Timed Systems. - Rüdiger Ehlers; Michael Gerke 002; Hans-Jörg Peter (ICFEM, 2010)

Fully Symbolic Timed Model Checking Using Constraint Matrix Diagrams. - Rüdiger Ehlers; Daniel Fass; Michael Gerke 002; Hans-Jörg Peter (RTSS, 2010)

Synthesising certificates in networks of timed automata. - Bernd Finkbeiner; Hans-Jörg Peter; Sven Schewe (IET Softw., 2010)

Synthia: Verification and Synthesis for Timed Automata. - Hans-Jörg Peter; Rüdiger Ehlers; Robert Mattmüller (CAV, 2011)

The Complexity of Bounded Synthesis for Timed Control with Partial Observability. - Hans-Jörg Peter; Bernd Finkbeiner (FORMATS, 2012)

FlexRay for Avionics: Automatic Verification with Parametric Physical Layers. - Michael Gerke 002; Rüdiger Ehlers; Bernd Finkbeiner; Hans-Jörg Peter (Infotech@Aerospace, 2012)

Template-Based Controller Synthesis for Timed Systems. - Bernd Finkbeiner; Hans-Jörg Peter (TACAS, 2012)

Can we build it: formal synthesis of control strategies for cooperative driver assistance systems. - Werner Damm; Hans-Jörg Peter; Jan-Hendrik Rakow; Bernd Westphal (Math. Struct. Comput. Sci., 2013)

A uniform approach to the complexity and analysis of succinct systems. - Hans-Jörg Peter (2013)

Conclusively verifying clock-domain crossings in very large hardware designs. - Guillaume Plassan; Hans-Jörg Peter; Katell Morin-Allory; Fahim Rahim; Shaker Sarwary; Dominique Borrione (VLSI-SoC, 2016)

Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings. - Guillaume Plassan; Hans-Jörg Peter; Katell Morin-Allory; Shaker Sarwary; Dominique Borrione (VLSI-SoC (Selected Papers), 2016)