A memory-based high-speed digital delay line with a large adjustable length. - Hans Jürgen Mattausch; Fred Matthiesen; Jutta Hartl; Reinhard Tielert; Erwin P. Jacobs (IEEE J. Solid State Circuits, 1988)

High performance of short-channel MOSFETs due to an elevated central-channel doping. - Masayasu Tanaka; N. Tokida; T. Okagaki; Mitiko Miura-Mattausch; Walter Hansch; Hans Jürgen Mattausch (ASP-DAC, 2000)

Correlation method of circuit-performance and technology fluctuations for improved design reliability. - D. Miyawaki; Shizunori Matsumoto; Hans Jürgen Mattausch; S. Ooshiro; Masami Suetake; Mitiko Miura-Mattausch; Shigetaka Kumashiro; Tetsuya Yamaguchi; Kyoji Yamashita; Noriaki Nakayama (ASP-DAC, 2001)

Test-circuit-based extraction of inter- and intra-chip MOSFET-performance variations for analog-design reliability. - Shizunori Matsumoto; Hans Jürgen Mattausch; S. Ooshiro; Y. Tatsumi; Mitiko Miura-Mattausch; Shigetaka Kumashiro; Terufumi Yamaguchi; Kyoji Yamashita; Noriaki Nakayama (CICC, 2001)

Circuit Simulation Models for Coming MOSFET Generations. - Mitiko Miura-Mattausch; Hiroaki Ueno; Hans Jürgen Mattausch; Shigetaka Kumashiro; Tetsuya Yamaguchi; Kyoji Yamashita; Noriaki Nakayama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Compact associative-memory architecture with fully parallel search capability for the minimum Hamming distance. - Hans Jürgen Mattausch; Takayuki Gyohten; Yoshihiro Soda; Tetsushi Koide (IEEE J. Solid State Circuits, 2002)

Temperature-independence-point properties for 0.1μm-scale pocket-implant technologies and the impact on circuit design. - Kazuya Hisamitsu; Hiroaki Ueno; Masayasu Tanaka; Daisuke Kitamaru; Mitiko Miura-Mattausch; Hans Jürgen Mattausch; Shigetaka Kumashiro; Tetsuya Yamaguchi; Kyoji Yamashita; Noriaki Nakayama (ASP-DAC, 2003)

A nearest-hamming-distance search memory with fully parallel mixed digital-analog match circuitry. - Tetsushi Koide; Hans Jürgen Mattausch; Yuji Yano; Takayuki Gyohten; Yoshihiro Soda (ASP-DAC, 2003)

A novel hierarchical multi-port cache. - Zhaomin Zhu; Koh Johguchi; Hans Jürgen Mattausch; Tetsushi Koide; Tai Hirakawa; Tetsuo Hironaka (ESSCIRC, 2003)

350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node. - Takashi Morimoto; Yohmei Harada; Tetsushi Koide; Hans Jürgen Mattausch (ASP-DAC, 2004)

Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors. - Tetsuya Sueyoshi; Hiroshi Uchida; Hans Jürgen Mattausch; Tetsushi Koide; Yosuke Mitani; Tetsuo Hironaka (ASP-DAC, 2004)

Associative memory with fully parallel nearest-Manhattan-distance search for low-power real-time single-chip applications. - Yuji Yano; Tetsushi Koide; Hans Jürgen Mattausch (ASP-DAC, 2004)

Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation. - Takashi Morimoto; Yohmei Harada; Tetsushi Koide; Hans Jürgen Mattausch (IEICE Trans. Inf. Syst., 2004)

A low-power video segmentation LSI with boundary-active-only architecture. - Takashi Morimoto; Osamu Kiriyama; Hidekazu Adachi; Zhaomin Zhu; Tetsushi Koide; Hans Jürgen Mattausch (ASP-DAC, 2005)

A parallel hardware design for parametric active contour models. - Ali Ahmadi; Md. Anwarul Abedin; Hans Jürgen Mattausch; Tetsushi Koide (AVSS, 2005)

MOSFET harmonic distortion analysis up to the non-quasi-static frequency regime. - Youichi Takeda; Dondee Navarro; Shingo Chiba; Mitiko Miura-Mattausch; Hans Jürgen Mattausch; Tatsuya Ohguro; Takahiro Iizuka; Masahiko Taguchi; Shigetaka Kumashiro; Shunsuke Miyamoto (CICC, 2005)

CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]. - Takeshi Kumaki; Yasuto Kuroda; Tetsushi Koide; Hans Jürgen Mattausch; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (ISCAS (5), 2005)

Object tracking in video pictures based on image segmentation and pattern matching. - Takashi Morimoto; Osamu Kiriyama; Yohmei Harada; Hidekazu Adachi; Tetsushi Koide; Hans Jürgen Mattausch (ISCAS (4), 2005)

Design of superscalar processor with multi-bank register file. - Tadashi Saito 002; Moto Maeda; Tetsuo Hironaka; Kazuya Tanigawa; Tetsuya Sueyoshi; Ken-ichi Aoyama; Tetsushi Koide; Hans Jürgen Mattausch (ISCAS (4), 2005)

A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features. - Kazunari Inoue; Hideyuki Noda; Kazutami Arimoto; Hans Jürgen Mattausch; Tetsushi Koide (IEICE Trans. Electron., 2005)

1/f-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation. - Shizunori Matsumoto; Hiroaki Ueno; Satoshi Hosokawa; Toshihiko Kitamura; Mitiko Miura-Mattausch; Hans Jürgen Mattausch; Tatsuya Ohguro; Shigetaka Kumashiro; Tetsuya Yamaguchi; Kyoji Yamashita; Noriaki Nakayama (IEICE Trans. Electron., 2005)

A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential. - Dondee Navarro; Takeshi Mizoguchi; Masami Suetake; Kazuya Hisamitsu; Hiroaki Ueno; Mitiko Miura-Mattausch; Hans Jürgen Mattausch; Shigetaka Kumashiro; Tetsuya Yamaguchi; Kyoji Yamashita; Noriaki Nakayama (IEICE Trans. Electron., 2005)

Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh. - Hideyuki Noda; Kazunari Inoue; Hans Jürgen Mattausch; Tetsushi Koide; Katsumi Dosaka; Kazutami Arimoto; Kazuyasu Fujishima; Kenji Anami; Tsutomu Yoshihara (IEICE Trans. Electron., 2005)

A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. - Hideyuki Noda; Kazunari Inoue; Masayuki Kuroiwa; Futoshi Igaue; Kouji Yamamoto 002; Hans Jürgen Mattausch; Tetsushi Koide; Atsushi Amo; Atsushi Hachisuka; Shinya Soeda; Isamu Hayashi; Fukashi Morishita; et al. (IEEE J. Solid State Circuits, 2005)

Chip size and performance evaluations of shared cache for on-chip multiprocessor. - Takahiro Sasaki; Tomohiro Inoue; Nobuhiko Omori; Tetsuo Hironaka; Hans Jürgen Mattausch; Tetsushi Koide (Syst. Comput. Jpn., 2005)

Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search. - Md. Anwarul Abedin; Yuki Tanaka; Ali Ahmadi; Tetsushi Koide; Hans Jürgen Mattausch (APCCAS, 2006)

Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline. - Koh Johguchi; Zhaomin Zhu; Hans Jürgen Mattausch; Tetsushi Koide; Tetsuo Hironaka; Kazuya Tanigawa (APCCAS, 2006)

Application of Multi-ported CAM for Parallel Coding. - Takeshi Kumaki; Y. Kouno; Masakatsu Ishizaki; Tetsushi Koide; Hans Jürgen Mattausch (APCCAS, 2006)

An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture. - Takashi Morimoto; Hidekazu Adachi; Kousuke Yamaoka; Kazutoshi Awane; Tetsushi Koide; Hans Jürgen Mattausch (APCCAS, 2006)

Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking. - Kousuke Yamaoka; Takashi Morimoto; Hidekazu Adachi; Tetsushi Koide; Hans Jürgen Mattausch (ASP-DAC, 2006)

A Learning OCR System Using Short/Long-term Memory Approach and Hardware Implementation in FPGA. - Ali Ahmadi; M. Arifin Ritonga; Md. Anwarul Abedin; Hans Jürgen Mattausch; Tetsushi Koide (IEEE Congress on Evolutionary Computation, 2006)

Multi-object tracking VLSI architecture using image-scan based region growing and feature matching. - Kousuke Yamaoka; Takashi Morimoto; Hidekazu Adachi; Kazutoshi Awane; Tetsushi Koide; Hans Jürgen Mattausch (ISCAS, 2006)

Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video-Segmentation. - Takashi Morimoto; Hidekazu Adachi; Osamu Kiriyama; Tetsushi Koide; Hans Jürgen Mattausch (IEICE Trans. Inf. Syst., 2006)

A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC. - Hideyuki Noda; Katsumi Dosaka; Hans Jürgen Mattausch; Tetsushi Koide; Fukashi Morishita; Kazutami Arimoto (IEICE Trans. Electron., 2006)

A 0.6-Tbps, 16-port SRAM design with 2-stage- pipeline and multi-stage-sensing scheme. - Koh Johguchi; Yuya Mukuda; Shinya Izumi; Hans Jürgen Mattausch; Tetsushi Koide (ESSCIRC, 2007)

Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. - Takeshi Kumaki; Tetsushi Koide; Hans Jürgen Mattausch; Yasuto Kuroda; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (ISCAS, 2007)

A 2-stage-pipelined 16 port SRAM with 590Gbps random access bandwidth and large noise margin. - Koh Johguchi; Yuya Mukuda; Ken-ichi Aoyama; Hans Jürgen Mattausch; Tetsushi Koide (IEICE Electron. Express, 2007)

Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories. - Md. Anwarul Abedin; Yuki Tanaka; Ali Ahmadi; Shogo Sakakibara; Tetsushi Koide; Hans Jürgen Mattausch (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words. - Koh Johguchi; Hans Jürgen Mattausch; Tetsushi Koide; Tetsuo Hironaka (IEICE Trans. Electron., 2007)

Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor. - Takeshi Kumaki; Masakatsu Ishizaki; Tetsushi Koide; Hans Jürgen Mattausch; Yasuto Kuroda; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (IEICE Trans. Inf. Syst., 2007)

Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory. - Takeshi Kumaki; Yutaka Kono; Masakatsu Ishizaki; Tetsushi Koide; Hans Jürgen Mattausch (IEICE Trans. Inf. Syst., 2007)

Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer. - Takeshi Kumaki; Yasuto Kuroda; Masakatsu Ishizaki; Tetsushi Koide; Hans Jürgen Mattausch; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (IEICE Trans. Inf. Syst., 2007)

The Physics and Modeling of Mosfets - Surface-Potential Model HiSIM - Mitiko Miura-Mattausch; Hans Jürgen Mattausch; Tatsuya Ezaki (World Scientific, 2008)

Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor. - Takeshi Kumaki; Masakatsu Ishizaki; Tetsushi Koide; Hans Jürgen Mattausch; Yasuto Kuroda; Takayuki Gyohten; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (IEICE Trans. Electron., 2008)

Compact Double-Gate Metal-Oxide-Semiconductor Field Effect Transistor Model for Device/Circuit Optimization. - Norio Sadachika; Takahiro Murakami; Hideki Oka; Ryou Tanabe; Hans Jürgen Mattausch; Mitiko Miura-Mattausch (IEICE Trans. Electron., 2008)

Non-quasi-static approach with surface-potential-based MOSFET model HiSIM for RF circuit simulations. - Tatsuya Ezaki; Dondee Navarro; Youichi Takeda; Norio Sadachika; Gaku Suzuki; Mitiko Miura-Mattausch; Hans Jürgen Mattausch; Tatsuya Ohguro; Takahiro Iizuka; Masahiko Taguchi; Shigetaka Kumashiro; Shunsuke Miyamoto (Math. Comput. Simul., 2008)

Non-Quasi-Static Carrier Dynamics of MOSFETs under Low-Voltage Operation. - Masataka Miyake; Daisuke Hori; Norio Sadachika; Uwe Feldmann; Mitiko Miura-Mattausch; Hans Jürgen Mattausch; Takahiro Iizuka; Kazuya Matsuzawa; Yasuyuki Sahara; Teruhiko Hoshida; Toshiro Tsukada (IEICE Trans. Electron., 2009)

Degraded Frequency-Tuning Range and Oscillation Amplitude of LC-VCOs due to the Nonquasi-Static Effect in MOS Varactors. - Masataka Miyake; Daisuke Hori; Norio Sadachika; Uwe Feldmann; Mitiko Miura-Mattausch; Hans Jürgen Mattausch; Tatsuya Ohguro; Takahiro Iizuka; Masahiko Taguchi; Shunsuke Miyamoto (IEICE Trans. Electron., 2009)

Low-power word-parallel nearest-Hamming-distance search circuit based on frequency mapping. - Hans Jürgen Mattausch; Wataru Imafuku; Tania Ansari; Akio Kawabata; Tetsushi Koide (ESSCIRC, 2010)

Optimization Vector Quantization by Adaptive Associative-Memory-Based Codebook Learning in Combination with Huffman Coding. - Akio Kawabata; Tetsushi Koide; Hans Jürgen Mattausch (ICNC, 2010)

Architecture and FPGA-Implementation of Scalable Picture Segmentation by 2D Scanning with Flexible Pixel-Block Size. - Tetsushi Koide; R. Kimura; T. Sugahara; K. Okazaki; Hans Jürgen Mattausch (ICNC, 2010)

A scalable massively parallel processor for real-time image processing. - Takashi Kurafuji; Masaru Haraguchi; Masami Nakajima; Takayuki Gyohten; Tetsu Nishijima; Hiroyuki Yamasaki; Yuta Imai; Masakatsu Ishizaki; Takeshi Kumaki; Yoshihiro Okuno; Tetsushi Koide; Hans Jürgen Mattausch; et al. (ISSCC, 2010)

Measurement-Based Ring Oscillator Variation Analysis. - Koh Johguchi; Akihiro Kaya; Shinya Izumi; Hans Jürgen Mattausch; Tetsushi Koide; Norio Sadachika (IEEE Des. Test Comput., 2010)

Real-time hybrid learning and recognition system with software-hardware cooperation. - Fengwei An; Hans Jürgen Mattausch; Tetsushi Koide (ROBIO, 2011)

An associative memory-based learning model with an efficient hardware implementation in FPGA. - Ali Ahmadi; Hans Jürgen Mattausch; Md. Anwarul Abedin; Mahmoud Saeidi; Tetsushi Koide (Expert Syst. Appl., 2011)

Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems. - Takeshi Kumaki; Tetsushi Koide; Hans Jürgen Mattausch; Masaharu Tagami; Masakatsu Ishizaki (IEICE Trans. Inf. Syst., 2011)

Prediction of Circuit-Performance Variations from Technology Variations for Reliable 100 nm SOC Circuit Design. - Norio Sadachika; Shu Mimura; Akihiro Yumisaki; Koh Johguchi; Akihiro Kaya; Mitiko Miura-Mattausch; Hans Jürgen Mattausch (IEICE Trans. Electron., 2011)

A Scalable Massively Parallel Processor for Real-Time Image Processing. - Takashi Kurafuji; Masaru Haraguchi; Masami Nakajima; Tetsu Nishijima; Tetsushi Tanizaki; Hiroyuki Yamasaki; Takeaki Sugimura; Yuta Imai; Masakatsu Ishizaki; Takeshi Kumaki; Kan Murata; Kanako Yoshida; et al. (IEEE J. Solid State Circuits, 2011)

Digital associative memory for word-parrallel Manhattan-distance-based vector quantization. - Seiryu Sasaki; Masahiro Yasuda; Hans Jürgen Mattausch (ESSCIRC, 2012)

Cluster-Based Prototype Learning System for Multiple Applications with Flexible HW/SW Codesign. - Fengwei An; Hans Jürgen Mattausch (PDCAT, 2012)

Human recognition with a hardware-accelerated multi-prototype learning and classification system. - Indra Bagus Wicaksono; Fengwei An; Hans Jürgen Mattausch (ROBIO, 2012)

A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching. - Fengwei An; Tetsushi Koide; Hans Jürgen Mattausch (IEICE Trans. Inf. Syst., 2012)

Compact Modeling of Expansion Effects in LDMOS. - Takahiro Iizuka; Takashi Sakuda; Yasunori Oritsuki; Akihiro Tanaka; Masataka Miyake; Hideyuki Kikuchihara; Uwe Feldmann; Hans Jürgen Mattausch; Mitiko Miura-Mattausch (IEICE Trans. Electron., 2012)

Associative Memory for Nearest-Hamming-Distance Search Based on Frequency Mapping. - Hans Jürgen Mattausch; Wataru Imafuku; Akio Kawabata; Tania Ansari; Masahiro Yasuda; Tetsushi Koide (IEEE J. Solid State Circuits, 2012)

Word-parallel coprocessor architecture for digital nearest Euclidean distance search. - Toshinobu Akazawa; Seiryu Sasaki; Hans Jürgen Mattausch (ESSCIRC, 2013)

Modeling of Trench-Gate Type HV-MOSFETs for Circuit Simulation. - Takahiro Iizuka; Kenji Fukushima; Akihiro Tanaka; Hideyuki Kikuchihara; Masataka Miyake; Hans Jürgen Mattausch; Mitiko Miura-Mattausch (IEICE Trans. Electron., 2013)

Modeling of NBTI Stress Induced Hole-Trapping and Interface-State-Generation Mechanisms under a Wide Range of Bias Conditions. - Chenyue Ma; Hans Jürgen Mattausch; Masataka Miyake; Takahiro Iizuka; Kazuya Matsuzawa; Seiichiro Yamaguchi; Teruhiko Hoshida; Akinori Kinoshita; Takahiko Arakawa; Jin He 003; Mitiko Miura-Mattausch (IEICE Trans. Electron., 2013)

K-means clustering algorithm for multimedia applications with flexible HW/SW co-design. - Fengwei An; Hans Jürgen Mattausch (J. Syst. Archit., 2013)

LVQ neural network SoC adaptable to different on-chip learning and recognition applications. - Fengwei An; Toshinobu Akazawa; Shogo Yamazaki; Lei Chen 001; Hans Jürgen Mattausch (APCCAS, 2014)

A coprocessor for clock-mapping-based nearest Euclidean distance search with feature vector dimension adaptability. - Fengwei An; Toshinobu Akazawa; Shogo Yamazaki; Lei Chen 001; Hans Jürgen Mattausch (CICC, 2014)

A SoPC architecture for nearest-neighbor based learning and recognition. - Fengwei An; Lei Chen 001; Hans Jürgen Mattausch (ISPACS, 2014)

Memory-based hardware-accelerated system for high-speed human detection. - Indra Bagus Wicaksono; Fengwei An; Hans Jürgen Mattausch (Adv. Robotics, 2014)

Compact Modeling of Injection Enhanced Insulated Gate Bipolar Transistor Valid for Optimization of Switching Frequency. - Takao Yamamoto; Masataka Miyake; Uwe Feldmann; Hans Jürgen Mattausch; Mitiko Miura-Mattausch (IEICE Trans. Electron., 2014)

Word-parallel associative memory for k-nearest-neighbor with configurable storage space of reference vectors. - Fengwei An; Keisuke Mihara; Shogo Yamazaki; Lei Chen 001; Hans Jürgen Mattausch (A-SSCC, 2015)

Mixed-domain compact modeling framework for fluid flow driven by electrostatic organic actuators. - Tapas Kumar Maiti; Lei Chen 001; Hidenori Miyamoto; Mitiko Miura-Mattausch; Hans Jürgen Mattausch (ESSDERC, 2015)

Pixel-based pipeline hardware architecture for high-performance Haar-like feature extraction. - Yuki Fujita; Fengwei An; Aiwen Luo; Xiangyu Zhang 002; Lei Chen 001; Hans Jürgen Mattausch (APCCAS, 2016)

Dynamically reconfigurable system for LVQ-based on-chip learning and recognition. - Fengwei An; Xiangyu Zhang 002; Lei Chen 001; Hans Jürgen Mattausch (ISCAS, 2016)

k Nearest Neighbor Classification Coprocessor with Weighted Clock-Mapping-Based Searching. - Fengwei An; Lei Chen 001; Toshinobu Akazawa; Shogo Yamazaki; Hans Jürgen Mattausch (IEICE Trans. Electron., 2016)

Actuator-Control Circuit Based on OTFTs and Flow-Rate Estimation for an All-Organic Fluid Pump. - Lei Chen 001; Tapas Kumar Maiti; Hidenori Miyamoto; Mitiko Miura-Mattausch; Hans Jürgen Mattausch (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Efficiency Analysis of SiC-MOSFET-Based Bidirectional Isolated DC/DC Converters. - Atsushi Saito; Kenshiro Sato; Yuta Tanimoto; Kai Matsuura; Yutaka Sasaki; Mitiko Miura-Mattausch; Hans Jürgen Mattausch; Yoshifumi Zoka (IEICE Trans. Electron., 2016)

A Memory-Based Modular Architecture for SOM and LVQ with Dynamic Configuration. - Fengwei An; Xiangyu Zhang 002; Lei Chen 001; Hans Jürgen Mattausch (IEEE Trans. Multi Scale Comput. Syst., 2016)

Compact modeling approach for electro-mechanical system simulation. - Tapas K. Maiti; Dondee Navarro; Mitiko Miura-Mattausch; Hans Jürgen Mattausch (ASICON, 2017)

Modeling of dynamic trap density increase for aging simulation of any MOSFET circuits. - Mitiko Miura-Mattausch; Hidenori Miyamoto; Hideyuki Kikuchihara; Dondee Navarro; Tapas K. Maiti; Nezam Rohbani; C. Ma; Hans Jürgen Mattausch; A. Schiffmann; Alexander Steinmair; Ehrenfried Seebacher (ESSDERC, 2017)

Modeling of Field-Plate Effect on Gallium-Nitride-Based High Electron Mobility Transistors for High-Power Applications. - Takeshi Mizoguchi; Toshiyuki Naka; Yuta Tanimoto; Yasuhiro Okada; Wataru Saito; Mitiko Miura-Mattausch; Hans Jürgen Mattausch (IEICE Trans. Electron., 2017)

Real-Time Straight-Line Detection for XGA-Size Videos by Hough Transform with Parallelized Voting Procedures. - Jungang Guan; Fengwei An; Xiangyu Zhang 002; Lei Chen 001; Hans Jürgen Mattausch (Sensors, 2017)

Compact Modeling for Power Efficient Circuit Design. - Mitiko Miura-Mattausch; Hideyuki Kikuchihara; Tahahiro Kajiwara; Yuta Tanimoto; Atsushi Saito; Takahiro Iizuka; Dondee Navarro; Hans Jürgen Mattausch (ESSDERC, 2018)

Fast Recognition and Control of Walking Mode for Humanoid Robot Based on Pressure Sensors and Nearest Neighbor Search. - Sandip Bhattacharya; Aiwen Luo; Tapas K. Maiti; Sunandan Dutta; Mitiko Miura-Mattausch; Hans Jürgen Mattausch (ISPACS, 2018)

Self-controlled walking robot with gyro sensor network for stable movement on non-smooth surfaces. - Sunandan Dutta; Tapas K. Maiti; Yoshihiro Ochi; Mitiko Miura-Mattausch; Sandip Bhattacharya; Dondee Navarro; Naoto Yorino; Hans Jürgen Mattausch (SIMPAR, 2018)

Compact modeling of dynamic trap density evolution for predicting circuit-performance aging. - Mitiko Miura-Mattausch; Hidenori Miyamoto; Hideyuki Kikuchihara; Tapas K. Maiti; Nezam Rohbani; Dondee Navarro; Hans Jürgen Mattausch (Microelectron. Reliab., 2018)

A Modular and Reconfigurable Pipeline Architecture for Learning Vector Quantization. - Xiangyu Zhang 002; Fengwei An; Lei Chen 001; Idaku Ishii; Hans Jürgen Mattausch (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A Hardware Architecture for Cell-Based Feature-Extraction and Classification Using Dual-Feature Space. - Fengwei An; Xiangyu Zhang 002; Aiwen Luo; Lei Chen 001; Hans Jürgen Mattausch (IEEE Trans. Circuits Syst. Video Technol., 2018)

Resource-Efficient Object-Recognition Coprocessor With Parallel Processing of Multiple Scan Windows in 65-nm CMOS. - Aiwen Luo; Fengwei An; Xiangyu Zhang 002; Lei Chen 001; Hans Jürgen Mattausch (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Dynamic Pattern-Recognition-Based Walking-Speed Adjustment for Stable Biped-Robot Movement under Changing Surface Conditions. - Aiwen Luo; Sandip Bhattacharya; Tapas Kumar Maiti; Sunandan Dutta; Yoshihiro Ochi; Mitiko Miura-Mattausch; Hans Jürgen Mattausch (GCCE, 2019)

NVDL-Cache: Narrow-Width Value Aware Variable Delay Low-Power Data Cache. - Nezam Rohbani; Tapas Kumar Maiti; Dondee Navarro; Mitiko Miura-Mattausch; Hans Jürgen Mattausch; Hirotaka Takatsuka (ICCD, 2019)

Stability Analysis of Humanoid Robots with Gyro Sensors Subjected to External Push Forces. - Sunandan Dutta; Tapas K. Maiti; Yoshihiro Ochi; Mitiko Miura-Mattausch; Sandip Bhattacharya; Naoto Yorino; Hans Jürgen Mattausch (ISDCS, 2019)

Validation on Duality in Impact-ionization Carrier Generation at the Onset of Snapback in Power MOSFETs. - Takahiro Iizuka; Hiroyuki Hashigami; Mitiko Miura-Mattausch; Hans Jürgen Mattausch (ISDCS, 2019)

Power Consumption Estimation of Biped Robot During Walking. - Tapas K. Maiti; Sunandan Dutta; Yoshihiro Ochi; Mitiko Miura-Mattausch; Sandip Bhattacharya; Hans Jürgen Mattausch (ISDCS, 2019)

Analysis of IGBT Charging/Discharging Mechanism for Accurate Compact Modeling. - Yosuke Miyaoku; Mitiko Miura-Mattausch; Akihiro Tone; Hans Jürgen Mattausch; Kai Matsuura; Daisaku Ikoma (ISDCS, 2019)

Analysis of Embedded-Diode Performance in MOSFET under Switching Condition. - Takao Yamamoto; Yukiya Fukunaga; Daisaku Ikoma; Mitiko Miura-Mattausch; Dondee Navarro; Hans Jürgen Mattausch (ISDCS, 2019)

Surface-Property Recognition With Force Sensors for Stable Walking of Humanoid Robot. - Sandip Bhattacharya; Aiwen Luo; Tapas Kumar Maiti; Sunandan Dutta; Yoshihiro Ochi; Mitiko Miura-Mattausch; Hans Jürgen Mattausch (IEEE Access, 2019)

A Hardware-Efficient Recognition Accelerator Using Haar-Like Feature and SVM Classifier. - Aiwen Luo; Fengwei An; Xiangyu Zhang 002; Hans Jürgen Mattausch (IEEE Access, 2019)

Energy-Efficient Hardware Implementation of Road-Lane Detection Based on Hough Transform with Parallelized Voting Procedure and Local Maximum Algorithm. - Jungang Guan; Fengwei An; Xiangyu Zhang 002; Lei Chen 001; Hans Jürgen Mattausch (IEICE Trans. Inf. Syst., 2019)

Prevention of Highly Power-Efficient Circuits due to Short-Channel Effects in MOSFETs. - Arnab Mukhopadhyay; Tapas Kumar Maiti; Sandip Bhattacharya; Takahiro Iizuka; Hideyuki Kikuchihara; Mitiko Miura-Mattausch; Hafizur Rahaman 001; Sadayuki Yoshitomi; Dondee Navarro; Hans Jürgen Mattausch (IEICE Trans. Electron., 2019)

Power Reduction and BTI Mitigation of Data-Cache Memory Based on the Storage Management of Narrow-Width Values. - Nezam Rohbani; Hiroaki Gau; Sara Mohammadinejad; Tapas Kumar Maiti; Dondee Navarro; Mitiko Miura-Mattausch; Hans Jürgen Mattausch; Hirotaka Takatsuka (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Surface Recognition and Speed Adjustment of Humanoid Robot Using External Control Circuit. - Sandip Bhattacharya; Aiwen Luo; Sunandan Dutta; Mitiko Miura-Mattausch; Hans Jürgen Mattausch (ISDCS, 2020)

History Effect on Circuit Performance of SOI-MOSFETs. - Soumajit Ghosh; Mitiko Miura-Mattausch; Takahiro Iizuka; Hideyuki Kikuchihara; Hafizur Rahaman 001; Hans Jürgen Mattausch (ISDCS, 2020)

Modeling of Short-Channel Effect on Multi-Gate MOSFETs for Circuit Simulation. - Fernando Ávila Herrera; Mitiko Miura-Mattausch; Takahiro Iizuka; Hideyuki Kikuchihara; Yoko Hirano; Hans Jürgen Mattausch (ISDCS, 2020)

Force-Sensor-Based Walking-Environment Recognition of Biped Robots. - Hans Jürgen Mattausch; Aiwen Luo; Sunandan Dutta; Sunandan Dutta; Tapas K. Maiti; Mitiko Miura-Mattausch (ISDCS, 2020)

Energy Efficiency of Force-Sensor-Controlled Humanoid-Robot Walking on Indoor Surfaces. - Sandip Bhattacharya; Sunandan Dutta; Aiwen Luo; Mitiko Miura-Mattausch; Yoshihiro Ochi; Hans Jürgen Mattausch (IEEE Access, 2020)

Force-Sensor-Based Surface Recognition With Surface-Property-Dependent Walking-Speed Adjustment of Humanoid Robot. - Sandip Bhattacharya; Aiwen Luo; Sunandan Dutta; Mitiko Miura-Mattausch; Hans Jürgen Mattausch (IEEE Access, 2020)

Analysis of Sensor-Based Real-Time Balancing of Humanoid Robots on Inclined Surfaces. - Sunandan Dutta; Tapas Kumar Maiti; Mitiko Miura-Mattausch; Yoshihiro Ochi; Naoto Yorino; Hans Jürgen Mattausch (IEEE Access, 2020)

Prediction of DC-AC Converter Efficiency Degradation due to Device Aging Using a Compact MOSFET-Aging Model. - Kenshiro Sato; Dondee Navarro; Shinya Sekizaki; Yoshifumi Zoka; Naoto Yorino; Hans Jürgen Mattausch; Mitiko Miura-Mattausch (IEICE Trans. Electron., 2020)

Gyro-Sensor-Based Vibration Control for Dynamic Humanoid-Robot Walking on Inclined Surfaces. - Sunandan Dutta; Mitiko Miura-Mattausch; Yoshihiro Ochi; Naoto Yorino; Hans Jürgen Mattausch (Sensors, 2020)

Modeling of SJ-MOSFET for High-Voltage Applications with Inclusion of Carrier Dynamics during Switching. - Hideyuki Kikuchihara; Mitiko Miura-Mattausch; Takeshi Mizoguchi; Hajime Nagase; Makoto Hashimoto; Yusuke Kawaguchi; Hans Jürgen Mattausch (ISDCS, 2021)

Model Development for Robust Design of SOI-MOSFET Circuits used in Radiative Environments. - Mitiko Miura-Mattausch; Hideyuki Kikuchihara; Hans Jürgen Mattausch (ISDCS, 2021)

Simulation-Based Power-Loss Optimization of General-Purpose High-Voltage SiC MOSFET Circuit Under High-Frequency Operation. - Abhishek Kar; Mitiko Miura-Mattausch; Mainak Sengupta; Dondee Navarro; Hideyuki Kikuchihara; Takahiro Iizuka; Hafizur Rahaman 001; Hans Jürgen Mattausch (IEEE Access, 2021)

Electro-mechanical Model and its Application to biped-robot stability with force Sensors. - Tapas K. Maiti; Sunandan Dutta; Yoshihiro Ochi; Mitiko Miura-Mattausch; Hans Jürgen Mattausch (Int. J. Robotics Autom., 2022)

Real-Time Surface Identification System for Variable Walking Speeds of Biped Robots. - Aiwen Luo; Sandip Bhattacharya; Mitiko Miura-Mattausch; Yicong Zhou; Hans Jürgen Mattausch (IEEE Embed. Syst. Lett., 2024)