A Technique for Synthesizing Distributed Burst-mode Circuits. - Prabhakar Kudva; Ganesh Gopalakrishnan; Hans M. Jacobson (DAC, 1996)

Synthesis for Hazard-free Customized CMOS Complex-Gate Networks Under Multiple-Input Changes. - Prabhakar Kudva; Ganesh Gopalakrishnan; Hans M. Jacobson; Steven M. Nowick (DAC, 1996)

Asynchronous Microengines for Efficient High-level Control. - Hans M. Jacobson; Ganesh Gopalakrishnan (ARVLSI, 1997)

Application-specific programmable control for high-performance asynchronous circuits. - Hans M. Jacobson; Ganesh Gopalakrishnan (Proc. IEEE, 1999)

Corrections To application-specific Programmable Control For High-performance Asynchronous Circuits. - Hans M. Jacobson; Ganesh Gopalakrishnan (Proc. IEEE, 1999)

High-Level Asynchronous System Design Using the ACK Framework. - Hans M. Jacobson; Erik Brunvand; Ganesh Gopalakrishnan; Prabhakar Kudva (ASYNC, 2000)

Achieving Fast and Exact Hazard-Free Logic Minimization of Extended Burst-Mode gC Finite State Machines. - Hans M. Jacobson; Chris J. Myers; Ganesh Gopalakrishnan (ICCAD, 2000)

Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors. - David M. Brooks; Pradip Bose; Stanley Schuster; Hans M. Jacobson; Prabhakar Kudva; Alper Buyuktosunoglu; John-David Wellman; Victor V. Zyuban; Manish Gupta; Peter W. Cook (IEEE Micro, 2000)

Efficient Exact Two-Level Hazard-Free Logic Minimization. - Chris J. Myers; Hans M. Jacobson (ASYNC, 2001)

Synchronous Interlocked Pipelines. - Hans M. Jacobson; Prabhakar Kudva; Pradip Bose; Peter W. Cook; Stanley Schuster (ASYNC, 2002)

Early-Stage Definition of LPX: A Low Power Issue-Execute Processor. - Pradip Bose; David M. Brooks; Alper Buyuktosunoglu; Peter W. Cook; K. Das; Philip G. Emma; Michael Gschwind; Hans M. Jacobson; Tejas Karkhanis; Prabhakar Kudva; Stanley Schuster; James E. Smith 001; et al. (PACS, 2002)

Efficient algorithms for exact two-level hazard-free logic minimization. - Hans M. Jacobson; Chris J. Myers (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Microarchitectural techniques for power gating of execution units. - Zhigang Hu; Alper Buyuktosunoglu; Viji Srinivasan; Victor V. Zyuban; Hans M. Jacobson; Pradip Bose (ISLPED, 2004)

Improved clock-gating through transparent pipelining. - Hans M. Jacobson (ISLPED, 2004)

Interlocked Synchronous Pipelines. - Hans M. Jacobson (2004)

Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors. - Hans M. Jacobson; Pradip Bose; Zhigang Hu; Alper Buyuktosunoglu; Victor V. Zyuban; Richard J. Eickemeyer; Lee Eisen; John Griswell; Doug Logan; Balaram Sinharoy; Joel M. Tendler (HPCA, 2005)

Power-efficient, reliable microprocessor architectures: modeling and design methods. - Pradip Bose; Alper Buyuktosunoglu; Chen-Yong Cher; John A. Darringer; Meeta Sharma Gupta; Hendrik F. Hamann; Hans M. Jacobson; Prabhakar Kudva; Eren Kursun; Niti Madan; Indira Nair; Jude A. Rivers; et al. (ACM Great Lakes Symposium on VLSI, 2010)

Abstraction and microarchitecture scaling in early-stage power modeling. - Hans M. Jacobson; Alper Buyuktosunoglu; Pradip Bose; Emrah Acar; Richard J. Eickemeyer (HPCA, 2011)

Power management of multi-core chips: Challenges and pitfalls. - Pradip Bose; Alper Buyuktosunoglu; John A. Darringer; Meeta Sharma Gupta; Michael B. Healy; Hans M. Jacobson; Indira Nair; Jude A. Rivers; Jeonghee Shin; Augusto Vega; Alan J. Weger (DATE, 2012)

Application-level power and performance characterization and optimization on IBM Blue Gene/Q systems. - Ramon Bertran; Yutaka Sugawara; Hans M. Jacobson; Alper Buyuktosunoglu; Pradip Bose (IBM J. Res. Dev., 2013)

Design for low power and power management in IBM Blue Gene/Q. - Krishnan Sugavanam; Chen-Yong Cher; John A. Gunnels; Ruud A. Haring; Philip Heidelberger; Hans M. Jacobson; Moyra K. McManus; D. P. Paulsen; David L. Satterfield; Yutaka Sugawara; Robert Walkup (IBM J. Res. Dev., 2013)

Empirically derived abstractions in uncore power modeling for a server-class processor chip. - Hans M. Jacobson; Arun Joseph; Dharmesh Parikh; Pradip Bose; Alper Buyuktosunoglu (ISLPED, 2014)

Quantifying sources of error in McPAT and potential impacts on architectural studies. - Sam Likun Xi; Hans M. Jacobson; Pradip Bose; Gu-Yeon Wei; David M. Brooks (HPCA, 2015)

Active Memory Cube: A processing-in-memory architecture for exascale systems. - Ravi Nair; Samuel Antão; Carlo Bertolli; Pradip Bose; José R. Brunheroto; Tong Chen 001; Chen-Yong Cher; Carlos H. A. Costa; J. Doi; Constantinos Evangelinos; Bruce M. Fleischer; Thomas W. Fox; et al. (IBM J. Res. Dev., 2015)

Very Low Voltage (VLV) Design. - Ramon Bertran; Pradip Bose; David M. Brooks; Jeff Burns; Alper Buyuktosunoglu; Nandhini Chandramoorthy; Eric Cheng; Martin Cochet; Schuyler Eldridge; Daniel Friedman; Hans M. Jacobson; Rajiv V. Joshi; et al. (ICCD, 2017)

Generation of Stressmarks for Early Stage Soft-Error Modeling. - Karthik Swaminathan; Ramon Bertran; Hans M. Jacobson; Prabhakar Kudva; Pradip Bose (DSN (Supplements), 2019)

SERMiner : A Framework for Early-stage Reliability Estimation for IBM Processors. - Karthik Swaminathan; Ramon Bertran; Hans M. Jacobson; Pradip Bose; Matthias Pflanz; Doug Balazich (DSN (Supplements), 2021)

Energy Efficiency Boost in the AI-Infused POWER10 Processor. - Brian W. Thompto; Dung Q. Nguyen; José E. Moreira; Ramon Bertran; Hans M. Jacobson; Richard J. Eickemeyer; Rahul M. Rao; Michael Goulet; Marcy Byers; Christopher J. Gonzalez; Karthik Swaminathan; Nagu R. Dhanwada; et al. (ISCA, 2021)

Characterization and Exploration of Latch Checkers for Efficient RAS Protection. - Karthik Swaminathan; Ramon Bertran; Doug Balazich; Alper Buyuktosunoglu; Arvind Haran; Sean M. Carey; Karl Anderson; Hans M. Jacobson; Matthias Pflanz; Pradip Bose (DSN-S, 2023)