Lateral NWFET optimization for beyond 7nm nodes. - Dmitry Yakimets; Doyoung Jang; Praveen Raghavan; Geert Eneman; Hans Mertens; P. Schuddinck; Arindam Mallik; Marie Garcia Bardon; Nadine Collaert; Abdelkarim Mercha; Diederik Verkest; Aaron Thean; et al. (ICICDT, 2015)

NBTI in Si0.55Ge0.45 cladding p-FinFETs: Porting the superior reliability from planar to 3D architectures. - Jacopo Franco; Ben Kaczer; Philippe J. Roussel; Erik Bury; Hans Mertens; Romain Ritzenthaler; Tibor Grasser; Naoto Horiguchi; Aaron Thean; Guido Groeseneken (IRPS, 2015)

PPAC scaling enablement for 5nm mobile SoC technology. - Mustafa Badaroglu; Jeff Xu; John Zhu; Da Yang 007; Jerry Bao; Seung Chul Song; Peijie Feng; Romain Ritzenthaler; Hans Mertens; Geert Eneman; Naoto Horiguchi; Jeffrey Smith 003; et al. (ESSDERC, 2017)

Isolation of nanowires made on bulk wafers by ground plane doping. - Romain Ritzenthaler; Hans Mertens; An De Keersgieter; Jérôme Mitard; Dan Mocuta; N. Horiguchi (ESSDERC, 2017)

Impact of Device Architecture and Gate Stack Processing on the Low-Frequency Noise of Silicon Nanowire Transistors. - Eddy Simoen; Alberto Vinicius Oliveira; Anabela Veloso; Adrian Vaisman Chasin; Romain Ritzenthaler; Hans Mertens; Naoto Horiguchi; Cor Claeys (ASICON, 2019)

CDM-Time Domain Turn-on Transient of ESD Diodes in Bulk FinFET and GAA NW Technologies. - Shih-Hung Chen; Dimitri Linten; Geert Hellings; Marko Simicic; Ben Kaczer; Thomas Chiarella; Hans Mertens; Jérôme Mitard; Anda Mocuta; N. Horiguchi (IRPS, 2019)

Full (Vg, Vd) Bias Space Modeling of Hot-Carrier Degradation in Nanowire FETs. - Michiel Vandemaele; Ben Kaczer; Stanislav Tyaginov; Zlatan Stanojevic; Alexander Makarov; Adrian Vaisman Chasin; Erik Bury; Hans Mertens; Dimitri Linten; Guido Groeseneken (IRPS, 2019)

The properties, effect and extraction of localized defect profiles from degraded FET characteristics. - Michiel Vandemaele; Ben Kaczer; Stanislav Tyaginov; Jacopo Franco; Robin Degraeve; Adrian Vaisman Chasin; Zhicheng Wu; Erik Bury; Yang Xiang; Hans Mertens; Guido Groeseneken (IRPS, 2021)

Evaluating Forksheet FET Reliability Concerns by Experimental Comparison with Co-integrated Nanosheets. - Erik Bury; Adrian Vaisman Chasin; Ben Kaczer; Michiel Vandemaele; Stanislav Tyaginov; Jacopo Franco; Romain Ritzenthaler; Hans Mertens; Pieter Weckx; N. Horiguchi; Dimitri Linten (IRPS, 2022)

Simulation Comparison of Hot-Carrier Degradation in Nanowire, Nanosheet and Forksheet FETs. - Michiel Vandemaele; Ben Kaczer; Stanislav Tyaginov; Erik Bury; Adrian Vaisman Chasin; Jacopo Franco; Alexander Makarov; Hans Mertens; Geert Hellings; Guido Groeseneken (IRPS, 2022)

Reliability challenges in Forksheet Devices: (Invited Paper). - Erik Bury; Michiel Vandemaele; Jacopo Franco; Adrian Chasin; Stanislav Tyaginov; A. Vandooren; Romain Ritzenthaler; Hans Mertens; Javier Diaz-Fortuny; N. Horiguchi; Dimitri Linten; Ben Kaczer (IRPS, 2023)

Investigating Nanowire, Nanosheet and Forksheet FET Hot-Carrier Reliability via TCAD Simulations: Invited Paper. - Michiel Vandemaele; Ben Kaczer; Erik Bury; Jacopo Franco; Adrian Chasin; Alexander Makarov; Hans Mertens; Geert Hellings; Guido Groeseneken (IRPS, 2023)

Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning. - Hans Mertens; M. Hosseini; Thomas Chiarella; D. Zhou; S. Wang; G. Mannaert; E. Dupuy; D. Radisic; Z. Tao; Yusuke Oniki; Andriy Hikavyy; R. Rosseel; et al. (VLSI Technology and Circuits, 2023)

Comparative Analysis of Uncertainty Quantification Models in Active Learning for Efficient System Identification of Dynamical Systems. - Hans Mertens; Frances Zhu (CASE, 2024)

Vt Fine-Tuning in Multi-Vt Gate-All-Around Nanosheet nFETs Using Rare-Earth Oxide-Based Dipole-First Gate Stack Compatible with CFET Integration. - Hiroaki Arimura; Hans Mertens; Jacopo Franco; L. Lukose; W. Maqsood; S. Brus; Thomas Chiarella; A. Impagnatiello; S. Homkar; V. K. Mootheri; C. Yin; G. Alessio Verni; et al. (VLSI Technology and Circuits, 2024)

Monolithic Complementary Field Effect Transistors (CFET) Demonstrated using Middle Dielectric Isolation and Stacked Contacts. - Steven Demuynck; Victor Vega-Gonzalez; C. Toledo de Carvalho Cavalcante; L. Petersen Barbosa Lima; K. Stiers; C. Sheng; A. Vandooren; M. Hosseini; X. Zhou; Hans Mertens; Thomas Chiarella; Jürgen Bömmels; et al. (VLSI Technology and Circuits, 2024)

Cost-Aware Query Policies in Active Learning for Efficient Autonomous Robotic Exploration. - Sapphira Akins; Hans Mertens; Frances Zhu (CoRR, 2024)