A CMOS analog continuous-time delay line with adaptive delay-time control. - Klaas Bult; Hans Wallinga (IEEE J. Solid State Circuits, 1988)

Design and analysis of CMOS analog signal processing circuits by means of a graphical MOST model. - Hans Wallinga; Klaas Bult (IEEE J. Solid State Circuits, 1989)

From specification to measurement: the bottleneck in analog industrial testing. - Robert Van Rijsinge; A. A. R. M. Haggenburg; C. de Vries; Hans Wallinga (ITC, 1990)

A nonvolatile analog programmable voltage source using the VIPMOS EEPROM structure. - Gijs van Steenwijk; Klaas Hoen; Hans Wallinga (IEEE J. Solid State Circuits, 1993)

A high-speed analog neural processor. - Peter Masa; Klaas Hoen; Hans Wallinga (IEEE Micro, 1994)

Learning behavior and temporary minima of two-layer neural networks. - Anne-Johan Annema; Klaas Hoen; Hans Wallinga (Neural Networks, 1994)

Analog weight adaptation hardware. - Anne-Johan Annema; Hans Wallinga (Neural Process. Lett., 1995)

A CMOS "soft-switched" transconductor and its application in gain control and filters. - Clemens H. J. Mensink; Bram Nauta; Hans Wallinga (IEEE J. Solid State Circuits, 1997)

Low-Frequency Noise Phenomena in Switched MOSFETs. - Arnoud P. van der Wel; Eric A. M. Klumperink; Jay S. Kolhatkar; Eric Hoekstra; Martijn F. Snoeij; Cora Salm; Hans Wallinga; Bram Nauta (IEEE J. Solid State Circuits, 2007)

Low-frequency noise in hot-carrier degraded nMOSFETs. - Cora Salm; Eric Hoekstra; Jay S. Kolhatkar; André J. Hof; Hans Wallinga; Jurriaan Schmitz (Microelectron. Reliab., 2007)