Static read stability and write ability metrics in FinFET based SRAM considering read and write-assist circuits. - Hanwool Jeong; Younghwi Yang; Junha Lee; Jisu Kim; Seong-Ook Jung (ICECS, 2012)

Impact of fin thickness and height on read stability / write ability in tri-gate FinFET based SRAM. - Junha Lee; Hanwool Jeong; Younghwi Yang; Jisu Kim; Seong-Ook Jung (ISOCC, 2012)

Pseudo NMOS based sense amplifier for high speed single-ended SRAM. - Hanwool Jeong; Taewon Kim; Seong-Ook Jung; Taejoong Song; Gyu-Hong Kim (ICECS, 2014)

One-Sided Static Noise Margin and Gaussian-Tail-Fitting Method for SRAM. - Hanwool Jeong; Younghwi Yang; Junha Lee; Jisu Kim; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Comparative Study of Various Latch-Type Sense Amplifiers. - Taehui Na; Seung-Han Woo; Jisu Kim; Hanwool Jeong; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Efficiency analysis of importance sampling in deep submicron STT-RAM design using uncontrollable industry-compatible model parameter. - Taehui Na; Hanwool Jeong; Seong-Ook Jung; Jung Pill Kim; Seung-Hyuk Kang (ICECS, 2015)

Switching pMOS Sense Amplifier for High-Density Low-Voltage Single-Ended SRAM. - Hanwool Jeong; Taewon Kim; Kyoman Kang; Taejoong Song; Gyu-Hong Kim; Hyo-Sig Won; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM. - Hanwool Jeong; Taewon Kim; Younghwi Yang; Taejoong Song; Gyu-Hong Kim; Hyo-Sig Won; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM. - Hanwool Jeong; Taewon Kim; Taejoong Song; Gyu-Hong Kim; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory. - Heechai Kang; Jisu Kim; Hanwool Jeong; Younghwi Yang; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM. - Hanwool Jeong; Juhyun Park; Tae Woo Oh; Woojin Rim; Taejoong Song; Gyu-Hong Kim; Hyo-Sig Won; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Transient Cell Supply Voltage Collapse Write Assist Using Charge Redistribution. - Ki-Ryong Kim; Hanwool Jeong; Juhyun Park; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology. - Younghwi Yang; Hanwool Jeong; Seung Chul Song; Joseph Wang; Geoffrey Yeap; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation. - Kyoman Kang; Hanwool Jeong; Younghwi Yang; Juhyun Park; Ki-Ryong Kim; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2016)

SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis. - Tae Hoon Choi; Hanwool Jeong; Younghwi Yang; Juhyun Park; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Pre-Charged Local Bit-Line Sharing SRAM Architecture for Near-Threshold Operation. - Tae Woo Oh; Hanwool Jeong; Juhyun Park; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Power-Gated 9T SRAM Cell for Low-Energy Operation. - Tae Woo Oh; Hanwool Jeong; Kyoman Kang; Juhyun Park; Younghwi Yang; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation. - Hanwool Jeong; Tae Woo Oh; Seung Chul Song; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A Voltage and Temperature Tracking SRAM Assist Supporting 740mV Dual-Rail Offset for Low-Power and High-Performance Applications in 7nm EUV FinFET Technology. - Inhak Lee; Hanwool Jeong; Sangyeop Baeck; Siddharth Gupta 008; Changnam Park; Dongwook Seo; Jaeseung Choi 001; Jaeyoung Kim; Hoon Kim; Jungmyung Kang; Sunyung Jang; Daeyoung Moon; et al. (ISSCC, 2019)

Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_{ mathrm{MIN}}$ Improvement and Energy Saving. - Hanwool Jeong; Se Hyeok Oh; Tae Woo Oh; Hoonki Kim; Changnam Park; Woojin Rim; Taejoong Song; Seong-Ook Jung (IEEE J. Solid State Circuits, 2019)

Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time. - Hanwool Jeong; Juhyun Park; Seung Chul Song; Seong-Ook Jung (IEEE J. Solid State Circuits, 2019)

An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache. - Tae Hyun Kim; Hanwool Jeong; Juhyun Park; Hoonki Kim; Taejoong Song; Seong-Ook Jung (IEEE Access, 2020)

High-Density SRAM Read Access Yield Estimation Methodology. - Gidong Baek; Hanwool Jeong (IEEE Access, 2021)

A Wide-Range Static Current-Free Current Mirror-Based LS With Logic Error Detection for Near-Threshold Operation. - Hanwool Jeong; Tae Hyun Kim; Changnam Park; Hoonki Kim; Taejoong Song; Seong-Ook Jung (IEEE J. Solid State Circuits, 2021)

All-Digital Time-Domain Temperature Sensor for Energy Efficient On-Chip Thermal Management. - Gidong Baek; Hanwool Jeong (ICEIC, 2022)

Self-Shut-Off Pulsed Latches for Minimizing Sequencing Overhead. - Hyunho Park; Hanwool Jeong (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Machine Learning-Based Read Access Yield Estimation and Design Optimization for High-Density SRAM. - Taehwan Yoon; Hanwool Jeong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Voltage Boosted Fail Detecting Circuit for Selective Write Assist and Cell Current Boosting for High-Density Low-Power SRAM. - Jaehyun Park 014; Sangheon Lee 005; Hanwool Jeong (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Energy-Efficient Wide-Range Level Shifter With a Logic Error Detection Circuit. - Jihwan Park; Hanwool Jeong (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Cross-Coupled nFET Preamplifier for Low Voltage SRAM. - Sangheon Lee 005; Jaehyun Park 014; Hanwool Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Bayesian Learning Automated SRAM Circuit Design for Power and Performance Optimization. - Junseo Lee; Jihwan Park; Seokhun Kim; Hanwool Jeong (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Design of High-Speed, Low-Power Sensing Circuits for Nano-Scale Embedded Memory. - Sangheon Lee 005; Gwanwoo Park; Hanwool Jeong (Sensors, 2024)

High Efficiency Variation-Aware SRAM Timing Characterization via Machine-Learning-Assisted Netlist Extraction. - Inseong Jeon; Hyunho Park; Taehwan Yoon; Hanwool Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Simultaneous Optimization of Various-Sized SRAM Instances Through Machine Learning-Driven Transistor Sizing and Leafcell Circuit Pool Construction. - Seokhun Kim; Junseo Lee; Dongho Kim; Jihwan Park; Sangheon Lee 005; Hanwool Jeong (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

Bayesian Learning-Enhanced Embedded Memory Design With Automated Circuit Variant Generation. - Dongho Kim; Junseo Lee; Seokhun Kim; Jihwan Park; Sangheon Lee 005; Hanwool Jeong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)