A 2.3 GHz 2.8 mW Sampling ΔΣ PLL Achieving -110 dBc/Hz In-Band Phase Noise and 500 MHz FMCW Chirp. - Hanyang Su; Jingcheng Tao; Siegfred D. Balon; Chun-Huat Heng (IEEE J. Solid State Circuits, 2021)