Towards a universal and portable assembly code size reduction: a case study of RISC-V ISA. - Jianfeng Liu; Wangrong Gao; Hanzheng Liang; Lin Peng; Ting Wang 009 (CCF Trans. High Perform. Comput., 2024)

An empirical performance evaluation of SYCL on ARM multi-core processors. - Hanzheng Liang; Chencheng Deng; Peng Zhang 061; Jianbin Fang; Tao Tang 001; Chun Huang (CCF Trans. High Perform. Comput., 2025)