Reliability aware design of low power continuous-time sigma-delta modulator. - Hao Cai 001; Hervé Petit; Jean-François Naviner (Microelectron. Reliab., 2011)

A Hierarchical Reliability Simulation Methodology for AMS Integrated Circuits and Systems. - Hao Cai 001; Hervé Petit; Jean-François Naviner (J. Low Power Electron., 2012)

Reliability analysis of combinational circuits with the influences of noise and single-event transients. - Kaikai Liu; Hao Cai 001; Ting An; Lirida A. B. Naviner; Jean-François Naviner; Hervé Petit (DFTS, 2013)

A general cost-effective design structure for probabilistic-based noise-tolerant logic functions in nanometer CMOS technology. - Kaikai Liu; Ting An; Hao Cai 001; Lirida A. B. Naviner; Jean-François Naviner; Hervé Petit (EUROCON, 2013)

A fast reliability-aware approach for analogue integrated circuits based on Pareto fronts. - Hao Cai 001; Hervé Petit; Jean-François Naviner (NEWCAS, 2013)

Efficient computation of combinational circuits reliability based on probabilistic transfer matrix. - Lirida A. B. Naviner; Kaikai Liu; Hao Cai 001; Jean-François Naviner (ICICDT, 2014)

Simulation study of aging in CMOS binary adders. - Ting An; Hao Cai 001; Lirida Alves de Barros Naviner (MIPRO, 2014)

Efficient implementation for accurate analysis of CED circuits against multiple faults. - Ting An; Kaikai Liu; Hao Cai 001; Lirida Alves de Barros Naviner (MIXDES, 2014)

Reliability-aware delay faults evaluation of CMOS flip-flops. - Hao Cai 001; Kaikai Liu; Lirida Alves de Barros Naviner (MIXDES, 2014)

Stochastic computation with Spin Torque Transfer Magnetic Tunnel Junction. - Lirida Alves de Barros Naviner; Hao Cai 001; You Wang 002; Weisheng Zhao; Arwa Ben Dhia (NEWCAS, 2015)

Accurate reliability analysis of concurrent checking circuits employing an efficient analytical method. - Ting An; Kaikai Liu; Hao Cai 001; Lirida A. B. Naviner (Microelectron. Reliab., 2015)

Cross-layer investigation of continuous-time sigma-delta modulator under aging effects. - Hao Cai 001; You Wang 002; Kaikai Liu; Lirida Alves de Barros Naviner; Hervé Petit; Jean-François Naviner (Microelectron. Reliab., 2015)

Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology. - Hao Cai 001; You Wang 002; Lirida A. B. Naviner; W. S. Zhao (Microelectron. Reliab., 2015)

A dual-rail compact defect-tolerant multiplexer. - Arwa Ben Dhia; Mariem Slimani; Hao Cai 001; Lirida A. B. Naviner (Microelectron. Reliab., 2015)

Compact thermal modeling of spin transfer torque magnetic tunnel junction. - You Wang 002; Hao Cai 001; Lirida A. B. Naviner; Yue Zhang 010; Jacques-Olivier Klein; Weisheng Zhao (Microelectron. Reliab., 2015)

Approximate computing in MOS/spintronic non-volatile full-adder. - Hao Cai 001; You Wang 002; Lirida A. B. Naviner; Zhaohao Wang; Weisheng Zhao (NANOARCH, 2016)

A novel circuit design of true random number generator using magnetic tunnel junction. - You Wang 002; Hao Cai 001; Lirida A. B. Naviner; Jacques-Olivier Klein; Jianlei Yang 001; Weisheng Zhao (NANOARCH, 2016)

Efficient reliability evaluation methodologies for combinational circuits. - Hao Cai 001; Kaikai Liu; Lirida Alves de Barros Naviner; You Wang 002; Mariem Slimani; Jean-François Naviner (Microelectron. Reliab., 2016)

Reliability analysis of hybrid spin transfer torque magnetic tunnel junction/CMOS majority voters. - Mariem Slimani; Paulo F. Butzen; Lirida A. B. Naviner; You Wang 002; Hao Cai 001 (Microelectron. Reliab., 2016)

A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI. - You Wang 002; Hao Cai 001; Lirida A. B. Naviner; Xiaoxuan Zhao; Yue Zhang 010; Mariem Slimani; Jacques-Olivier Klein; Weisheng Zhao (Microelectron. Reliab., 2016)

Energy Efficient Magnetic Tunnel Junction Based Hybrid LSI Using Multi-Threshold UTBB-FD-SOI Device. - Hao Cai 001; You Wang 002; Lirida A. B. Naviner; Wang Kang 001; Weisheng Zhao (ACM Great Lakes Symposium on VLSI, 2017)

Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core. - Hao Cai 001; You Wang 002; Lirida A. B. Naviner; Weisheng Zhao (ISVLSI, 2017)

Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology. - Hao Cai 001; You Wang 002; Lirida Alves de Barros Naviner; Weisheng Zhao (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Stability and Variability Emphasized STT-MRAM Sensing Circuit With Performance Enhancement. - Menglin Han; Hao Cai 001; Jun Yang 006; Lirida A. B. Naviner; You Wang 002; Weisheng Zhao (APCCAS, 2018)

Reliability Emphasized MTJ/CMOS Hybrid Circuit Towards Ultra-Low Power. - Hao Cai 001; Menglin Han; You Wang 002; Lirida A. B. Naviner; Xinning Liu; Jun Yang 006; Weisheng Zhao (DCIS, 2018)

Design Space Exploration of Magnetic Tunnel Junction based Stochastic Computing in Deep Learning. - You Wang 002; Yue Zhang 010; Youguang Zhang; Weisheng Zhao; Hao Cai 001; Lirida A. B. Naviner (ACM Great Lakes Symposium on VLSI, 2018)

Compressed Sensing for Wideband HF Channel Estimation. - Elaine Crespo Marques; Nilson Maciel; Lirida A. B. Naviner; Hao Cai 001; Jun Yang 006 (ICFSP, 2018)

Enabling Resilient Voltage-Controlled MeRAM Using Write Assist Techniques. - Hao Cai 001; You Wang 002; Wang Kang 001; Lirida A. B. Naviner; Weiwei Shan; Jun Yang 006; Weisheng Zhao (ISCAS, 2018)

MRAM-on-FDSOI Integration: A Bit-Cell Perspective. - Hao Cai 001; You Wang 002; Wang Kang 001; Lirida A. B. Naviner; Xinning Liu; Jun Yang 006; Weisheng Zhao (ISVLSI, 2018)

A Robust Dual Reference Computing-in-Memory Implementation and Design Space Exploration Within STT-MRAM. - Liuyang Zhang; Wang Kang 001; Hao Cai 001; Peng Ouyang; Lionel Torres; Youguang Zhang; Aida Todri-Sanial; Weisheng Zhao (ISVLSI, 2018)

Correlation-Based Electromagnetic Analysis Attack Using Haar Wavelet Reconstruction with Low-Pass Filtering on an FPGA Implementaion of AES. - Aiguo Bu; Wentao Dai; Minyi Lu; Hao Cai 001; Weiwei Shan (TrustCom/BigDataSE, 2018)

A high-reliability and low-power computing-in-memory implementation within STT-MRAM. - Liuyang Zhang; Erya Deng; Hao Cai 001; You Wang 002; Lionel Torres; Aida Todri-Sanial; Youguang Zhang (Microelectron. J., 2018)

Single-event transient effects on dynamic comparator in 28 nm FDSOI CMOS technology. - Nilson Maciel; Elaine Crespo Marques; Lirida A. B. Naviner; Hao Cai 001 (Microelectron. Reliab., 2018)

HTD: A Light-Weight Holosymmetrical Transition Detector for Wide-Voltage-Range Variation Resilient ICs. - Wentao Dai; Weiwei Shan; Xinchao Shang; Xinning Liu; Hao Cai 001; Jun Yang 006 (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Voltage-Controlled Magnetoelectric Memory Bit-cell Design With Assisted Body-bias in FD-SOI. - Hao Cai 001; Menglin Han; Weiwei Shan; Jun Yang 006; You Wang 002; Wang Kang 001; Weisheng Zhao (ACM Great Lakes Symposium on VLSI, 2019)

Deep Learning Approaches for Sparse Recovery in Compressive Sensing. - Elaine Crespo Marques; Nilson Maciel; Lirida A. B. Naviner; Hao Cai 001; Jun Yang 006 (ISPA, 2019)

Pj-AxMTJ: Process-in-memory with Joint Magnetization Switching for Approximate Computing in Magnetic Tunnel Junction. - Hao Cai 001; Honglan Jiang; Menglin Han; Zhaohao Wang; You Wang 002; Jun Yang 006; Jie Han 001; Leibo Liu; Weisheng Zhao (ISVLSI, 2019)

Comprehensive Pulse Shape Induced Failure Analysis in Voltage-Controlled MRAM. - Mingyue Liu; Hao Cai 001; Menglin Han; Lei Xie; Jun Yang 006; Lirida A. B. Naviner (NANOARCH, 2019)

REAL: Logic and Arithmetic Operations Embedded in RRAM for General-Purpose Computing. - Lei Xie; Hao Cai 001; Jun Yang 006 (NANOARCH, 2019)

A Self-Timing Voltage-Mode Sense Amplifier for STT-MRAM Sensing Yield Improvement. - Yongliang Zhou; Menglin Han; Mingyue Liu; Hao Cai 001; Bo Liu 019; Jun Yang 006 (NANOARCH, 2019)

Nonlinear Functions in Learned Iterative Shrinkage-Thresholding Algorithm for Sparse Signal Recovery. - Elaine Crespo Marques; Nilson Maciel; Lirida A. B. Naviner; Hao Cai 001; Jun Yang 006 (SiPS, 2019)

A Review of Sparse Recovery Algorithms. - Elaine Crespo Marques; Nilson Maciel; Lirida A. B. Naviner; Hao Cai 001; Jun Yang 006 (IEEE Access, 2019)

Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration. - Hao Cai 001; You Wang 002; Lirida Alves de Barros Naviner; Xinning Liu; Weiwei Shan; Jun Yang 006; Weisheng Zhao (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Wide-Voltage-Range Half-Path Timing Error-Detection System With a 9-Transistor Transition-Detector in 40-nm CMOS. - Weiwei Shan; Xinchao Shang; Xing Wan; Hao Cai 001; Chuan Zhang 001; Jun Yang 006 (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

An Ultra-low Power Keyword-Spotting Accelerator Using Circuit-Architecture-System Co-design and Self-adaptive Approximate Computing Based BWN. - Bo Liu 019; Yuhao Sun; Hao Cai 001; Zeyu Shen 003; Yu Gong 002; Lepeng Huang; Zhen Wang 019 (ACM Great Lakes Symposium on VLSI, 2020)

A Learning-Based Timing Prediction Framework for Wide Supply Voltage Design. - Wei Bao; Peng Cao 002; Hao Cai 001; Aiguo Bu (ACM Great Lakes Symposium on VLSI, 2020)

A Modeling Attack Resilient Physical Unclonable Function Based on STT-MRAM. - Zhengyi Hou; You Wang 002; Deming Zhang; Chengzhi Wang; Hao Cai 001 (ACM Great Lakes Symposium on VLSI, 2020)

A Background Noise Self-adaptive VAD Using SNR Prediction Based Precision Dynamic Reconfigurable Approximate Computing. - Bo Liu 019; Yan Li 056; Lepeng Huang; Hao Cai 001; Wentao Zhu; Shisheng Guo; Yu Gong 002; Zhen Wang 019 (ACM Great Lakes Symposium on VLSI, 2020)

Magnetic Tunnel Junction-based Analog-to-Digital Converter using Spin Orbit Torque Mechanism. - Nilson Maciel; Elaine Crespo Marques; Lírida A. B. Naviner; Hao Cai 001 (ICECS, 2020)

Binarized Weight Neural-Network Inspired Ultra-Low Power Speech Recognition Processor with Time-Domain Based Digital-Analog Mixed Approximate Computing. - Bo Liu 019; Hao Cai 001; Yu Gong 002; Wentao Zhu; Yan Li 056; Wei Ge; Zhen Wang 019 (ISCAS, 2020)

Interplay Bitwise Operation in Emerging MRAM for Efficient In-memory Computing. - Hao Cai 001; Honglan Jiang; Yongliang Zhou; Menglin Han; Bo Liu 019 (CCF Trans. High Perform. Comput., 2020)

Towards an automated design flow for memristor based VLSI circuits. - Lei Xie; Hao Cai 001; Chao Wang 068; Jun Yang 006 (Integr., 2020)

TG-SPP: A One-Transmission-Gate Short-Path Padding for Wide-Voltage-Range Resilient Circuits in 28-nm CMOS. - Weiwei Shan; Wentao Dai; Chuan Zhang 001; Hao Cai 001; Peiye Liu; Jun Yang 006; Longxing Shi (IEEE J. Solid State Circuits, 2020)

Magnetic Tunnel Junction Applications. - Nilson Maciel; Elaine Crespo Marques; Lirida A. B. Naviner; Yongliang Zhou; Hao Cai 001 (Sensors, 2020)

A 22nm, 10.8 μ W/15.1 μ W Dual Computing Modes High Power-Performance-Area Efficiency Domained Background Noise Aware Keyword- Spotting Processor. - Bo Liu 019; Hao Cai 001; Zhen Wang 019; Yuhao Sun; Zeyu Shen 003; Wentao Zhu; Yan Li 056; Yu Gong 002; Wei Ge; Jun Yang 006; Longxing Shi (IEEE Trans. Circuits Syst., 2020)

MTJ-LRB: Proposal of MTJ-Based Loop Replica Bitline as MRAM Device-Circuit Interaction for PVT-Robust Sensing. - Yongliang Zhou; Hao Cai 001; Bo Liu 019; Weisheng Zhao; Jun Yang 006 (IEEE Trans. Circuits Syst., 2020)

A Self-Timed Voltage-Mode Sensing Scheme With Successive Sensing and Checking for STT-MRAM. - Yongliang Zhou; Hao Cai 001; Lei Xie; Menglin Han; Mingyue Liu; Shi Xu; Bo Liu 019; Weisheng Zhao; Jun Yang 006 (IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020)

Modified Peripheral MRAM Sensing for In-memory Boolean Logic. - Zhong-Jian Bian; Xiaofeng Hong; Juntong Chen; Hao Cai 001 (ASICON, 2021)

A Novel Hybrid Nonvolatile SRAM for Suppressing Leakage Power Using Tunnel FET. - Xiaofeng Hong; Hao Cai 001 (ASICON, 2021)

Ultra-low Power Access Strategy for Process-Voltage-Temperature Aware STT-MRAM. - You-You Zhang; Lirida A. B. Naviner; Hao Cai 001 (ASICON, 2021)

A 1D-CRNN Inspired Reconfigurable Processor for Noise-robust Low-power Keywords Recognition. - Bo Liu 019; Zeyu Shen 003; Lepeng Huang; Yu Gong 002; Zilong Zhang; Hao Cai 001 (DATE, 2021)

In-MRAM Computing Elements with Single-Step Convolution and Fully Connected for BNN/TNN. - Zhong-Jian Bian; Yanan Guo 004; Bo Liu 019; Hao Cai 001 (ICTA, 2021)

Analytical Delay Model in Near-Threshold Domain Considering Transition Time. - Haiyang Jiang 014; Bingqian Xu; Peng Cao 002; Hao Cai 001 (ICTA, 2021)

Cryogenic In-MRAM Computing. - Yaoru Hou; We Ge; Yanan Guo 004; Lirida A. B. Naviner; You Wang 002; Bo Liu 019; Jun Yang 006; Hao Cai 001 (NANOARCH, 2021)

Hybrid MTJ-CMOS Integration for Sigma-Delta ADC. - Yu-ang Wu; Lirida A. B. Naviner; Hao Cai 001 (NANOARCH, 2021)

A survey of in-spin transfer torque MRAM computing. - Hao Cai 001; Bo Liu 019; Juntong Chen; Lirida A. B. Naviner; Yongliang Zhou; Zhen Wang 019; Jun Yang 006 (Sci. China Inf. Sci., 2021)

A 510-nW Wake-Up Keyword-Spotting Chip Using Serial-FFT-Based MFCC and Binarized Depthwise Separable CNN in 28-nm CMOS. - Weiwei Shan; Minhao Yang; Tao Wang; Yicheng Lu; Hao Cai 001; Lixuan Zhu; Jiaming Xu; Chengjun Wu; Longxing Shi; Jun Yang 006 (IEEE J. Solid State Circuits, 2021)

Toward Energy-Efficient STT-MRAM Design With Multi-Modes Reconfiguration. - Hao Cai 001; Juntong Chen; Yongliang Zhou; Weisheng Zhao (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Spintronic Solutions for Approximate Computing. - You Wang 002; Hao Cai 001; Kaili Zhang; Bo Wu; Bo Liu 019; Deming Zhang; Weisheng Zhao (Approximate Computing, 2022)

Approximate Computing for Energy-Constrained DNN-Based Speech Recognition. - Bo Liu 019; Hao Cai 001; Zhen Wang 019; Jun Yang 006 (Approximate Computing, 2022)

Triple-Skipping Near-MRAM Computing Framework for AIoT Era. - Juntong Chen; Hao Cai 001; Bo Liu 019; Jun Yang 006 (DATE, 2022)

A Target-Separable BWN Inspired Speech Recognition Processor with Low-power Precision-adaptive Approximate Computing. - Bo Liu 019; Hao Cai 001; Xuan Zhang; Haige Wu; Anfeng Xue; Zilong Zhang; Zhen Wang 019; Jun Yang 006 (DATE, 2022)

A CGP-based Efficient Approximate Multiplier with Error Compensation. - Qiao Shen 001; Renyuan Zhang; Hao Zhang 111; Hao Cai 001; Bo Liu 019; Jian Xiao (ICTA, 2022)

Towards Near LLC Speed STT-MRAM Sensing Using Reconfigurable Clock Trimming. - Xiaoyun Tian; Zhongjian Bian; Hao Cai 001 (ICTA, 2022)

A TWN Inspired Speaker Verification Processor with Hardware-friendly Weight Quantization. - Xuanhao Zhang; Haige Wu; Renyuan Zhang; Zihang Xu; Hao Zhang 111; Bo Liu 019; Hao Cai 001 (ICTA, 2022)

A Low Power DNN-based Speech Recognition Processor with Precision Recoverable Approximate Computing. - Bo Liu 019; Xuetao Wang; Renyuan Zhang; Anfeng Xue; Ziyu Wang; Haige Wu; Hao Cai 001 (ISCAS, 2022)

Low-cost stochastic number generator based on MRAM for stochastic computing. - You Wang 002; Bi Wu 002; Hao Cai 001; Weiqiang Liu 001 (NANOARCH, 2022)

Self-compensation tensor multiplication unit for adaptive approximate computing in low-power CNN processing. - Bo Liu 019; Zilong Zhang; Hao Cai 001; Reyuan Zhang; Zhen Wang 019; Jun Yang 006 (Sci. China Inf. Sci., 2022)

Bit-error-rate aware sensing-error correction interaction in spintronic MRAM. - Hao Cai 001; Xinfang Tong; Pengcheng Wu; Xinning Liu; Bo Liu 019 (J. Syst. Archit., 2022)

An Efficient BCNN Deployment Method Using Quality-Aware Approximate Computing. - Bo Liu 019; Ziyu Wang; Xuetao Wang; Renyuan Zhang; Anfeng Xue; Qiao Shen 001; Na Xie; Yu Gong 002; Zhen Wang 019; Jun Yang 006; Hao Cai 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Proposal of Analog In-Memory Computing With Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell. - Hao Cai 001; Yanan Guo 004; Bo Liu 019; Mingyang Zhou 002; Juntong Chen; Xinning Liu; Jun Yang 006 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Quality Driven Systematic Approximation for Binary-Weight Neural Network Deployment. - Yu Gong 002; Hao Cai 001; Haige Wu; Wei Ge; Hao Yan 002; Zhen Wang 019; Longxing Shi; Bo Liu 019 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

More is Less: Domain-Specific Speech Recognition Microprocessor Using One-Dimensional Convolutional Recurrent Neural Network. - Bo Liu 019; Hao Cai 001; Zilong Zhang; Xiaoling Ding; Ziyu Wang; Yu Gong 002; Weiqiang Liu 001; Jinjiang Yang; Zhen Wang 019; Jun Yang 006 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Machine Learning Attack-Resilient Strong PUF Leveraging the Process Variation of MRAM. - Rashid Ali; Deming Zhang; Hao Cai 001; Weisheng Zhao; You Wang 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Writing-only in-MRAM computing paradigm for ultra-low power applications. - Bo Liu 019; Mingyue Liu; Yongliang Zhou; Xiaofeng Hong; Hao Cai 001; Lirida Alves de Barros Naviner (Microprocess. Microsystems, 2022)

Work-in-Process: Error-Compensation-Based Energy-Efficient MAC Unit for CNNs. - Xingyu Xu 008; Qingwen Wei; Yang Zhang 132; Hao Cai 001; Bo Liu 019 (CASES, 2023)

Temperature-Adaptive MRAM Sensing Using Varied Magneto-Resistance. - Jiongzhe Su; Hao Zhang 111; Hao Cai 001 (ICTA, 2023)

Spice-Compatible Modeling of Double Barrier MTJ for Highly Reliable Circuits. - You Wang 002; Yefan Xu; Chaoyue Zhang; Yu Gong 002; Hao Cai 001; Weiqiang Liu 001 (ICTA, 2023)

An Energy-Efficient MAC Design with Error Compensation Using Hybrid Approximate Logic Synthesis. - Qingwen Wei; Yang Zhang 132; Xingyu Xu 008; Hao Cai 001; Bo Liu 019 (ICTA, 2023)

A FinFET Integrated STT-MRAM with Triple Balanced Access Strategy. - Xinshu Xie; Jiongzhe Su; Hao Zhang 111; Hao Cai 001 (ICTA, 2023)

A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference. - Hao Cai 001; Zhongjian Bian; Yaoru Hou; Yongliang Zhou; Jia-Le Cui; Yanan Guo 004; Xiaoyun Tian; Bo Liu 019; Xin Si; Zhen Wang 019; Jun Yang 006; Weiwei Shan (ISSCC, 2023)

A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs. - An Guo 001; Xin Si; Xi Chen 107; Fangyuan Dong; Xingyu Pu; Dongqi Li; Yongliang Zhou; Lizheng Ren; Yeyang Xue; Xueshan Dong; Hui Gao; Yiran Zhang; et al. (ISSCC, 2023)

A Reconfigurable Approximate Computing Architecture With Dual-VDD for Low-Power Binarized Weight Network Deployment. - Bo Liu 019; Anfeng Xue; Ziyu Wang; Na Xie; Xuetao Wang; Zhen Wang 019; Hao Cai 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Survey of MRAM-Centric Computing: From Near Memory to In Memory. - Yueting Li; Tianshuo Bai; Xinyi Xu; Yundong Zhang; Bi Wu 002; Hao Cai 001; Biao Pan; Weisheng Zhao (IEEE Trans. Emerg. Top. Comput., 2023)

AAD-KWS: A Sub-μ W Keyword Spotting Chip With an Acoustic Activity Detector Embedded in MFCC and a Tunable Detection Window in 28-nm CMOS. - Weiwei Shan; Junyi Qian; Lixuan Zhu; Jun Yang 006; Cheng Huang 005; Hao Cai 001 (IEEE J. Solid State Circuits, 2023)

Dependable STT-MRAM With Emerging Approximation and Speculation Paradigms. - Hao Cai 001; Yaoru Hou; Mengdi Zhang; Bo Liu 019; Lirida Alves de Barros Naviner (IEEE Des. Test, 2023)

Multiplication Circuit Architecture for Error- Tolerant CNN-Based Keywords Speech Recognition. - Bo Liu 019; Hao Cai 001; Zilong Zhang; Xiaoling Ding; Renyuan Zhang; Yu Gong 002; Zhen Wang 019; Wei Ge; Jun Yang 006 (IEEE Des. Test, 2023)

Computing in-memory with cascaded spintronic devices for AI edge. - Zhongjian Bian; Bo Liu 019; Hao Cai 001 (Comput. Electr. Eng., 2023)

W-AMA: Weight-aware Approximate Multiplication Architecture for neural processing. - Bo Liu 019; Renyuan Zhang; Qiao Shen 001; Zeju Li; Na Xie; Yuanhao Wang 009; Chonghang Xie; Hao Cai 001 (Comput. Electr. Eng., 2023)

Unveiling Security MRAM-OTP Macro using MTJ Hard Breakdown Mechanism. - Jiongzhe Su; Haoran Du; Quanhai Zhu; Mingtao Chen; Keyang Zhang; Bo Liu 019; Hao Cai 001 (AsianHOST, 2024)

Truly Random Number Generation by Using in-Plane Magnetic Tunnel Junction with Weak Anisotropy. - You Wang 002; Chaoyue Zhang; Yefan Xu; Yu Gong 002; Hao Cai 001; Weiqiang Liu 001 (AsianHOST, 2024)

A 28nm 128-kb Exponent- and Mantissa-Computation-InMemory Dual-macro for Floating-point and INT CNNs. - An Guo 001; Xueshan Dong; Fangyuan Dong; Dongqi Li; Yiran Zhang; Jingmin Zhang; Yuchen Tang; Yuhui Shi; Xiao Tan 001; Bo Liu 019; Weiwei Shan; Hao Cai 001; et al. (A-SSCC, 2024)

FDCA: Fine-grained Digital-CIM based CNN Accelerator with Hybrid Quantization and Weight-Stationary Dataflow. - Bo Liu 019; Qingwen Wei; Yang Zhang 132; Xingyu Xu 008; Zihan Zou; Xinxiang Huang; Xin Si; Hao Cai 001 (DAC, 2024)

Small-Footprint Automatic Speech Recognition System using Two-Stage Transfer Learning based Symmetrized Ternary Weight Network. - Xuanhao Zhang; Hui Kou; Chenjie Xia; Hao Cai 001; Bo Liu 019 (ICASSP, 2024)

22 nm Ultra-Low Power MCU with 43.5nW/KB Sleep Retention Power for Automotive Grade-1 Applications. - Yibo Liu; Wen Wang; Hongjin Zhu; Longning Qi; Bo Liu 019; Xinning Liu; Jun Yang 006; Hao Cai 001 (ICTA, 2024)

An Index-free Coding Compression Mechanism for Vision Transformers. - Han Yan; Zihan Zou; Shikuang Chen; Chen Zhang 025; Guang Yang 036; Hao Cai 001; Bo Liu 019 (ICTA, 2024)

Cache-Like Dual-Port SOT-MRAM with Read-while-Write Access Strategy. - Keyang Zhang; Bo Liu 019; Hao Cai 001 (ICTA, 2024)

Live Demonstration: A Target-Separable BWN Inspired Speech Recognition Processor with Low-power Precision-adaptive Approximate Computing. - Chenjie Xia; Xuanhao Zhang; Zihan Zou; Hao Cai 001; Bo Liu 019 (ISCAS, 2024)

Complementary Series-connected STT-MTJ for Time-based Computing-in-Memory. - Rong Zhou; Bo Liu 019; Xin Si; Hao Cai 001 (ISCAS, 2024)

34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs. - An Guo 001; Xi Chen 107; Fangyuan Dong; Jinwu Chen; Zhihang Yuan; Xing Hu 010; Yuanpeng Zhang 002; Jingmin Zhang; Yuchen Tang; Zhican Zhang; Gang Chen 023; Dawei Yang; et al. (ISSCC, 2024)

Towards Reliability MRAM for Energy-Efficient Spin-orbit Torque Switching. - Zhenghan Fang; Lirida Naviner; Wen Wang; Wei Le; Hao Cai 001 (SBCCI, 2024)

Sparsity-Oriented MRAM-Centric Computing for Efficient Neural Network Inference. - Jia-Le Cui; Yanan Guo 004; Juntong Chen; Bo Liu 019; Hao Cai 001 (IEEE Trans. Emerg. Top. Comput., 2024)

A CFMB STT-MRAM-Based Computing-in-Memory Proposal With Cascade Computing Unit for Edge AI Devices. - Yongliang Zhou; Zixuan Zhou; Yiming Wei; Zhen Yang; Xiao Lin; Chenghu Dai; Licai Hao; Chunyu Peng; Hao Cai 001; Xiulong Wu (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

VoAD: A Sub-μW Multiscene Voice Activity Detector Deploying Analog-Frontend Digital-Backend Circuits. - Yu Gong 002; Bo Liu 019; Hao Cai 001; Longxing Shi; Weiqiang Liu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Intrinsic MRAM Properties Enable Security Circuits. - Haoran Du; You Wang 002; Jun Yang 006; Hao Cai 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

On-Chip-Registration Supported ASR Processor Using Two-Step Transfer-Learning TWN. - Bo Liu 019; Xuanhao Zhang; Hui Kou; Chenjie Xia; Zhen Wang 019; Hao Cai 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Layer-Sensitive Neural Processing Architecture for Error-Tolerant Applications. - Zeju Li; Qinfan Wang; Zihan Zou; Qiao Shen 001; Na Xie; Hao Cai 001; Hao Zhang 111; Bo Liu 019 (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Low-Overhead Triple-Node-Upset Self-Recoverable Latch Design for Ultra-Dynamic Voltage Scaling Application. - Xin Chen 039; Yuxin Bai; Hao Cai 001; Congyi Zhu; Xinjie Zhou; Ying Zhang 068; Weiqiang Liu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Layer-Wise Mixed-Modes CNN Processing Architecture With Double-Stationary Dataflow and Dimension-Reshape Strategy. - Bo Liu 019; Xinxiang Huang; Yang Zhang 132; Guang Yang 036; Han Yan; Chen Zhang 025; Zejv Li; Yuanhao Wang 009; Hao Cai 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Timing Error Tolerant CNN Accelerator With Layerwise Approximate Multiplication. - Bo Liu 019; Na Xie; Qingwen Wei; Guang Yang 036; Chonghang Xie; Weiqiang Liu 001; Hao Cai 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

SUArch: Accelerating Layer-wise N: M Sparse Pattern with a Unified Architecture for Deep-learning Edge Device. - Xilong Kang; Qingwen Wei; Ningyuan Li 004; Xingyu Xu 008; Hao Cai 001; Bo Liu 019 (ASP-DAC, 2025)

AmPEC: Approximate MRAM with Partial Error Correction for Fine-grained Energy-quality Trade-off. - Lan-yang Sun; Yaoru Hou; Hao Cai 001 (ASP-DAC, 2025)

TWDP: A Vision Transformer Accelerator with Token-Weight Dual-Pruning Strategy for Edge Device Deployment. - Guang Yang 036; Xinming Yan; Hui Kou; Zihan Zou; Qingwen Wei; Hao Cai 001; Bo Liu 019 (ASP-DAC, 2025)

A 40nm 4Mb High-Reliability STT-MRAM Achieving 18ns Write-Time and 94.9% Wafer-Level-Die-Yield Across -55°C-to-125°C. - Yaoru Hou; Haoran Du; Jiongzhe Su; Yibo Liu; Zhenghan Fang; Jia-Le Cui; Shuyu Wang; Chenxing Liu-Sun; Xuezhao Wu; Zhihua Xiao; Bo Liu 019; Xin Si; et al. (CICC, 2025)

A 52.03TOPS/W DCIM-Based Accelerator with FlashAttention and Sparsity-Aware Alignment for LLMs. - Bo Liu 019; Xingyu Xu 008; Yang Zhang 132; Xilong Kang; Qingwen Wei; Zihan Zou; Jun Yang 006; Hao Cai 001; Xin Si (CICC, 2025)

OutlierCIM: Outlier-Aware Digital CIM-Based LLM Accelerator with Hybrid-Strategy Quantization and Unified FP-INT Computation. - Zihan Zou; Shikuang Chen; Chen Zhang 001; Xing Wang; Zhichao Liu; Haoran Du; Xin Si; Hao Cai 001; Bo Liu 019 (DAC, 2025)

A Hardware Prototype of an MRAM-based Stochastic Computing System. - Zhengkun Yu; Tianhan Fei; Hao Cai 001; Heng Shi; Yumeng Yang; Siting Liu 001 (ACM Great Lakes Symposium on VLSI, 2025)

14.6 A 28nm 64kb Bit-Rotated Hybrid-CIM Macro with an Embedded Sign-Bit-Processing Array and a Multi-Bit-Fusion Dual-Granularity Cooperative Quantizer. - Xi Chen 107; Shaochen Li; Zhican Zhang; Wentao Zheng; Xiao Tan 001; Yuchen Tang; Yuhui Shi; Lizheng Ren; Yibo Mai; Feiran Liu; Jinwu Chen; Zhaoyang Zhang; et al. (ISSCC, 2025)

14.7 NeuroPilot: A 28nm, 69.4fJ/node and 0.22ns/node, 32×32 Mimetic-Path-Searching CIM-Macro with Dynamic-Logic Pilot PE and Dual-Direction Searching. - An Guo 001; Jingmin Zhang; Xingyu Pu; Yi Yang 001; Defa Wu; Yuchen Tang; Yuhui Shi; Yinghai Gao; Zhichao Liu; Bo Wang 023; Tianzhu Xiong; Zhaoyang Zhang; et al. (ISSCC, 2025)

14.3 A 28nm 17.83-to-62.84TFLOPS/W Broadcast-Alignment Floating-Point CIM Macro with Non-Two's-Complement MAC for CNNs and Transformers. - Xing Wang; Tianhui Jiao; Yi Yang 001; Shaochen Li; Dongqi Li; An Guo 001; Yuhui Shi; Yuchen Tang; Jinwu Chen; Zhican Zhang; Zhichao Liu; Bo Liu 019; et al. (ISSCC, 2025)

Serial Magnetoresistance Accumulation Supported Spiking Neural Network in STT-MRAM. - Xiaoyun Tian; Zhongjian Bian; Bo Liu 019; Xin Si; Hao Cai 001 (NewCAS, 2025)

Reference-Free Single-Ended Spin-Transfer Torque MRAM with Low-Power Sensing. - Miao Yu; Shuyu Wang; Xiaoyun Tian; Hao Cai 001 (NewCAS, 2025)

Energy Efficient On-Chip Memory for Next Generation MCU. - Longning Qi; Jinqi Fan; Tongheng Rao; Meiyan Lv; Jingu Ma; Hao Cai 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

KV-Cache Oriented Query-Aware Sparse Attention Accelerator With Cross-Stage Precision-Configurable Digital CIM. - Yang Zhang 132; Xilong Kang; Weixuan Wang; Yizhi Ding; Lizheng Ren; Yiran Zhang; Ruiqi Tan; Zhen Wang 019; Hao Cai 001; Bo Liu 019 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

PF²A-ViT: Parameter-Free and Feature-Aware Dynamic Token Pruning Accelerator With Complementary Quantization-Encoding for Vision Transformer. - Zihan Zou; Xinming Yan; Chen Zhang 025; Shikuang Chen; Guang Yang 036; Han Yan; Hao Cai 001; Bo Liu 019 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)