A memory yield improvement scheme combining built-in self-repair and error correction codes. - Tze-Hsin Wu; Po-Yuan Chen; Mincent Lee; Bin-Yen Lin; Cheng-Wen Wu; Chen-Hung Tien; Hung-Chih Lin; Hao Chen 053; Ching-Nen Peng; Min-Jer Wang (ITC, 2012)

Test-yield improvement of high-density probing technology using optimized metal backer with plastic patch. - Sen-Kuei Hsu; Hao Chen 053; Chung-Han Huang; Der-Jiann Liu; Wei-Hsun Lin; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (ITC, 2013)

Wafer Level Chip Scale Package copper pillar probing. - Hao Chen 053; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (ITC, 2014)

A novel DFT architecture for 3DIC test, diagnosis and repair. - Mincent Lee; Saman Adham; Min-Jer Wang; Ching-Nen Peng; Hung-Chih Lin; Sen-Kuei Hsu; Hao Chen 053 (VLSI-DAT, 2014)

Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package. - Yu-Chieh Huang; Bing-Yang Lin; Cheng-Wen Wu; Mincent Lee; Hao Chen 053; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (DAC, 2016)

Fan-out wafer level chip scale package testing. - Hao Chen 053; Hung-Chih Lin; Min-Jer Wang (ITC-Asia, 2017)

Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package. - Kai-Li Wang; Bing-Yang Lin; Cheng-Wen Wu; Mincent Lee; Hao Chen 053; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang (IEEE Des. Test, 2017)

High Quality Test Methodology for Highly Reliable Devices. - Hao Chen 053; Mincent Lee; Liang-Yen Chen; Min-Jer Wang (ITC, 2019)

Site-aware Anomaly Detection with Machine Learning for Circuit Probing to Prevent Overkill. - Mincent Lee; Cheng-Tse Lu; Chia-Heng Tsai; Hao Chen 053; Min-Jer Wang (ITC-Asia, 2020)

Novel Circuit Probing for Tiny Inductor. - Chia-Heng Tsai; Chi-Chang Lai; Hao Chen 053; Min-Jer Wang (ITC-Asia, 2020)

A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices. - Chien-Hui Chuang; Kuan-Wei Hou; Cheng-Wen Wu; Mincent Lee; Chia-Heng Tsai; Hao Chen 053; Min-Jer Wang (ITC, 2020)