On-chip Analog Response Extraction with 1-Bit ? - Modulators. - Hao-Chiao Hong; Jiun-Lang Huang; Kwang-Ting Cheng; Cheng-Wen Wu (Asian Test Symposium, 2002)

Practical considerations in applying Σ-Δ modulation-based analog BIST to sampled-data systems. - Hao-Chiao Hong; Jiun-Lang Huang; Kwang-Ting Cheng; Cheng-Wen Wu; Ding-Ming Kwai (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

A Signa-Delta Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor for Diagnosis Purpose. - Hao-Chiao Hong; Cheng-Wen Wu; Kwang-Ting Cheng (Asian Test Symposium, 2004)

Design-for-digital-testability 30 MHz second-order Σ-Δ modulator. - Hao-Chiao Hong (CICC, 2004)

A Cost Effective Output Response Analyzer for sum - delta Modulation Based BIST Systems. - Hao-Chiao Hong; Sheng-Chuan Liang (ATS, 2006)

A Fully-Settled Linear Behavior Plus Noise Model for Evaluating the Digital Stimuli of the Design-for-Digital-Testability Sigma-Delta Modulators. - Hao-Chiao Hong (J. Electron. Test., 2007)

A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC. - Hao-Chiao Hong; Guo-Ming Lee (IEEE J. Solid State Circuits, 2007)

A Design-for-Digital-Testability Circuit Structure for Sigma-Delta Modulators. - Hao-Chiao Hong (IEEE Trans. Very Large Scale Integr. Syst., 2007)

A Cost Effective BIST Second-Order Sigma-Delta-Modulator. - Hao-Chiao Hong; Sheng-Chuan Liang; Hong-Chin Song (DDECS, 2008)

A Low-Cost Output Response Analyzer for the Built-in-Self-Test S-? Modulator Based on the Controlled Sine Wave Fitting Method. - Shao-Feng Hung; Hao-Chiao Hong; Sheng-Chuan Liang (Asian Test Symposium, 2009)

A Built-in-Self-Test Sigma-Delta ADC Prototype. - Hao-Chiao Hong; Sheng-Chuan Liang; Hong-Chin Song (J. Electron. Test., 2009)

A Decorrelating Design-for-Digital-Testability Scheme for Sigma-Delta Modulators. - Hao-Chiao Hong; Sheng-Chuan Liang (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A Fully Integrated Built-In Self-Test Sigma-Delta ADC Based on the Modified Controlled Sine-Wave Fitting Procedure. - Hao-Chiao Hong; Fang-Yi Su; Shao-Feng Hung (IEEE Trans. Instrum. Meas., 2010)

A Digitally Testable Sigma -Delta Modulator Using the Decorrelating Design-for-Digital-Testability. - Sheng-Chuan Liang; Hao-Chiao Hong (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Testing the Fleischer-Laker switched-capacitor biquad using the diagnosis-after-test procedure. - Shao-Feng Hung; Long-Yi Lin; Hao-Chiao Hong (ISOCC, 2012)

Experimental Results of Testing a BIST Σ-Δ ADC on the HOY Wireless Test Platform. - Shao-Feng Hung; Hao-Chiao Hong (J. Electron. Test., 2012)

A Static Linear Behavior Analog Fault Model for Switched-Capacitor Circuits. - Hao-Chiao Hong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Design of a Fault-Injectable Fleischer-Laker Switched-Capacitor Biquad for Verifying the Static Linear Behavior Fault Model. - Long-Yi Lin; Hao-Chiao Hong (Asian Test Symposium, 2013)

A Cost-Effective Stimulus Generator for Battery Channel Characterization in Electric Vehicles. - Shao-Feng Hung; Long-Yi Lin; Hao-Chiao Hong (ATS, 2014)

A fast-locking all-digital phase locked loop in 90nm CMOS for Gigascale systems. - Yi-Wei Chen; Hao-Chiao Hong (ISCAS, 2014)

A 17-nW, 0.5V, 500S/s, rail-to-rail SAR ADC with 8.1 effective number of bits. - Rong-Zhou Kuo; Hao-Chiao Hong (VLSI-DAT, 2014)

A Fully Integrated BIST ( Delta Sigma ) ADC Using the In-Phase and Quadrature Waves Fitting Procedure. - Shao-Feng Hung; Hao-Chiao Hong (IEEE Trans. Instrum. Meas., 2014)

14 GSps Four-Bit Noninterleaved Data Converter Pair in 90 nm CMOS With Built-In Eye Diagram Testability. - Hao-Chiao Hong; Yung-Shun Chen; Wei-Chieh Fang (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A Study on the Transfer Function Based Analog Fault Model for Linear and Time-Invariant Continuous-Time Analog Circuits. - Hao-Chiao Hong; Long-Yi Lin (ATS, 2016)

Gm-C filter with automatic calibration scheme. - Hong-Yi Huang; Kun-Yuan Chen; Jia-Hao Xie; Ming-Ta Lee; Hao-Chiao Hong; Kuo-Hsing Cheng (DDECS, 2016)

Low-voltage indoor energy harvesting using photovoltaic cell. - Hong-Yi Huang; Shao-Zu Yen; Jhen-Hong Chen; Hao-Chiao Hong; Kuo-Hsing Cheng (DDECS, 2016)

An Enhanced Boundary Scan Architecture for Inter-Die Interconnect Leakage Measurement in 2.5D and 3D Packages. - Pok Man Preston Law; Cheng-Wen Wu; Long-Yi Lin; Hao-Chiao Hong (ATS, 2017)

A 0.20-V to 0.25-V, Sub-nW, Rail-to-Rail, 10-bit SAR ADC for Self-Sustainable IoT Applications. - Hao-Chiao Hong; Yi Chiu (ISCAS, 2018)

A Digital Background Calibration Scheme for Pipelined ADCs Using Multiple-Correlation Estimation. - Meng-Shuan Wu; Hao-Chiao Hong (ISCAS, 2018)

A Wireless Gauge Pressure Sensor with Enhanced Sensitivity Fabricated by Flexible PCB Technology For Intracranial Pressure Sensing. - Yi Chiu; You-Zen Chen; Chia-Chun Hsieh; Hao-Chiao Hong (IEEE SENSORS, 2019)

Multiple Correlation Estimation Based Digital Background Calibration Scheme for Pipelined ADCs. - Kun-Chih Wu; Meng-Shuan Wu; Hao-Chiao Hong (ISCAS, 2019)

Accurate and Fast On-Wafer Test Circuitry for Device Array Characterization in Wafer Acceptance Test. - Hao-Chiao Hong; Long-Yi Lin (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Design of a 0.20-0.25-V, Sub-nW, Rail-to-Rail, 10-bit SAR ADC for Self-Sustainable IoT Applications. - Hao-Chiao Hong; Long-Yi Lin; Yi Chiu (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Interleaved Write Scheme for Improving Sequential Write Throughput of Multi-Chip MLC NAND Flash Memory Systems. - Hao-Chiao Hong; Chih-Ko Yang (IEEE Trans. Circuits Syst., 2020)

Accurate and Fast On-Wafer Test Circuitry Integrated With a 140-dB-Input-Range Current Digitizer for Parameter Tests in WAT. - Long-Yi Lin; Hao-Chiao Hong (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

CMOS MEMS Resonator for Physical Reservoir Computing. - Yi Chiu; Fang-Wei Tsai; Liang-Kai Wang; Yuan-Chieh Lee; Manu Garg; Hao-Chiao Hong (SENSORS, 2023)

Parametric Faults in Computing-in-Memory Applications of a 4kb Read-Decoupled 8T SRAM Array in 40nm CMOS. - Hao-Chiao Hong; Chien-Hung Chen; Yu-Wun Chen (ITC-Asia, 2023)

8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips. - Jian-Wei Su; Pei-Jung Lu; Ping-Chun Wu; Yen-Chi Chou; Ta-Wei Liu; Yen-Lin Chung; Li-Yang Hung; Jin-Sheng Ren; Wei-Hsing Huang; Chih-Han Chien; Peng-I Mei; Sih-Han Li; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Neuromorphic Spiking Neural Network Using Time-to-First-Spike Coding Scheme and Analog Computing in Low-Leakage 8T SRAM. - Chao-Yu Chen; Yan-Siou Dai; Hao-Chiao Hong (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A Reference-less All-digital BPSK-based Clock and Data Recovery Circuitry for Die-to-Die Interfaces. - Yi-Ting Yang; Hao-Chiao Hong; Kuo-Hsing Cheng (ISCAS, 2025)