Thermal simulator of 3D-IC with modeling of anisotropic TSV conductance and microchannel entrance effects. - Hanhua Qian; Hao Liang 003; Chip-Hong Chang; Wei Zhang 012; Hao Yu 001 (ASP-DAC, 2013)

A real-time QKD system based on FPGA - Hong-Fei Zhang; Jian Wang; Ke Cui; Chun-Li Luo; Sheng-zhao Lin; Lei Zhou; Hao Liang 003; Teng-Yun Chen; Kai Chen 008; Jian-Wei Pan (CoRR, 2013)

Hierarchical library-based power estimator for versatile FPGAs (abstract only). - Hao Liang 003; Yi-Chung Chen; Wei Zhang 012; Hai Li 001 (FPGA, 2014)

Reconfigurable DSP block design for dynamically reconfigurable architecture. - Rakesh Warrier; Hao Liang 003; Wei Zhang 012 (ISCAS, 2014)

Static hardware task placement on multi-context FPGA using hybrid genetic algorithm. - Hao Liang 003; Sharad Sinha; Rakesh Warrier; Wei Zhang 012 (FPL, 2015)

Hierarchical library based power estimator for versatile FPGAs. - Hao Liang 003; Wei Zhang 012; Sharad Sinha; Yi-Chung Chen; Hai Li 001 (FPL, 2015)

Hierarchical Library Based Power Estimator for Versatile FPGAs. - Hao Liang 003; Yi-Chung Chen; Tao Luo 014; Wei Zhang 012; Hai Li 001; Bingsheng He (MCSoC, 2015)

Leveraging Hotspots and Improving Chip Reliability via Carbon Nanotube Grid Thermal Structure. - Hao Liang 003; Wei Zhang 012; Jiale Huang; Shengqi Yang; Pallav Gupta (IEEE Trans. Very Large Scale Integr. Syst., 2015)

FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates. - Yijin Guan; Hao Liang 003; Ningyi Xu; Wenqiang Wang; Shaoshuai Shi; Xi Chen 107; Guangyu Sun 003; Wei Zhang 012; Jason Cong (FCCM, 2017)

HeteroSim: A Heterogeneous CPU-FPGA Simulator. - Liang Feng 001; Hao Liang 003; Sharad Sinha; Wei Zhang 012 (IEEE Comput. Archit. Lett., 2017)

A Hybrid Logic Block Architecture in FPGA for Holistic Efficiency. - Tao Luo 014; Hao Liang 003; Wei Zhang 012; Bingsheng He; Douglas L. Maskell (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A Collaborative Framework for FPGA-based CNN Design Modeling and Optimization. - Jiandong Mu; Wei Zhang 012; Hao Liang 003; Sharad Sinha (FPL, 2018)

Parallelizing Hardware Tasks on Multicontext FPGA With Efficient Placement and Scheduling Algorithms. - Hao Liang 003; Sharad Sinha; Wei Zhang 012 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors. - Zhe Lin 007; Sharad Sinha; Hao Liang 003; Liang Feng 001; Wei Zhang 012 (IEEE Trans. Multi Scale Comput. Syst., 2018)

PAI-FCNN: FPGA Based Inference System for Complex CNN Models. - Lixue Xia; Lansong Diao; Zhao Jiang; Hao Liang 003; Kai Chen 008; Li Ding; Shunli Dou; Zibin Su; Meng Sun; Jiansong Zhang 001; Wei Lin 016 (ASAP, 2019)

PAI-FCNN: FPGA Based CNN Inference System. - Lansong Diao; Zhao Jiang; Hao Liang 003; Chang'an Ye; Kai Chen 008; Li Ding; Shunli Dou; Meng Sun; Lixue Xia; Jiansong Zhang 001; Wei Lin 016 (FPGA, 2019)

Ouroboros: An Inference Engine for Deep Learning Based TTS on Embedded Devices. - Jiansong Zhang 001; Lixue Xia; Zhao Jiang; Hao Liang 003; Jiaoyan Chen; Shouda Liu; Wei Lin 016; Yuan Xie 001 (Hot Chips Symposium, 2019)

Optimizing OpenCL-Based CNN Design on FPGA with Comprehensive Design Space Exploration and Collaborative Performance Modeling. - Jiandong Mu; Wei Zhang 012; Hao Liang 003; Sharad Sinha (ACM Trans. Reconfigurable Technol. Syst., 2020)

Graph Sampling with Fast Random Walker on HBM-enabled FPGA Accelerators. - Chunyou Su; Hao Liang 003; Wei Zhang 012; Kun Zhao; Baole Ai; Wenting Shen; Zeke Wang (FPL, 2021)

RECom: A Compiler Approach to Accelerating Recommendation Model Inference with Massive Embedding Columns. - Zaifeng Pan; Zhen Zheng; Feng Zhang 007; Ruofan Wu; Hao Liang 003; Dalin Wang; Xiafei Qiu; Junjie Bai; Wei Lin 016; Xiaoyong Du 001 (ASPLOS (4), 2023)

ROMA: a Read-Only-Memory-based Accelerator for QLoRA-based On-Device LLM. - Wenqiang Wang; Yijia Zhang; Zikai Zhang; Guanting Huo; Hao Liang 003; Shijie Cao; Ningyi Xu (CoRR, 2025)