A high-speed CMOS track/hold circuit. - Mohd Asmawi Mohamed Zin; Haruo Kobayashi 001; Kazuya Kobayashi; Jun-ichi Ichimura; Hao San; Yoshitaka Onaya; Yasuyuki Kimura; Yasushi Yuminaka; Yoshisato Sasaki; Kouji Tanaka; Fuminori Abe (ICECS, 1999)

An Element Rotation Algorithm for Multi-bit DAC Nonlinearities in Complex Bandpass Delta SigmaAD Modulators. - Hao San; Haruo Kobayashi 001; Shinya Kawakami; Nobuyuki Kuroiwa (VLSI Design, 2004)

Reducing Spurious Output of Balanced Modulators by Dynamic Matching of I, Q Quadrature Paths. - Jun Otsuki; Hao San; Haruo Kobayashi 001; Takanori Komuro; Yoshihisa Yamada; Aiyan Liu (IEICE Trans. Electron., 2005)

Complex Bandpass DeltaSigmaAD Modulator Architecture without I, Q-Path Crossing Layout. - Hao San; Akira Hayakawa; Yoshitaka Jingu; Hiroki Wada; Hiroyuki Hagiwara; Kazuyuki Kobayashi; Haruo Kobayashi 001; Tatsuji Matsuura; Kouichi Yahagi; Junya Kudoh; Hideo Nakane; Masao Hotta; et al. (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

A 2.8-V Multibit Complex Bandpass Delta-Sigma-AD Modulator in 0.18µm CMOS. - Hao San; Yoshitaka Jingu; Hiroki Wada; Hiroyuki Hagiwara; Akira Hayakawa; Haruo Kobayashi 001; Masao Hotta (ASP-DAC, 2007)

A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA Algorithm. - Hao San; Yoshitaka Jingu; Hiroki Wada; Hiroyuki Hagiwara; Akira Hayakawa; Haruo Kobayashi 001; Tatsuji Matsuura; Kouichi Yahagi; Junya Kudoh; Hideo Nakane; Masao Hotta; Toshiro Tsukada; et al. (IEICE Trans. Electron., 2007)

ΔΣAD modulator for low power application. - Hajime Konagaya; HaiJun Lin; Hao San; Haruo Kobayashi 001; Kazumasa Ando; Hiroshi Yoshida; Chieto Murayama; Yukihiro Nisida (APCCAS, 2008)

High-resolution DPWM generator for digitally controlled DC-DC converters. - Ibuki Mori; Keigo Kimura; Yoshihisa Yamada; Haruo Kobayashi 001; Yasunori Kobori; Santhos Ario Wibowo; Kazuya Shimizu; Masashi Kono; Hao San (APCCAS, 2008)

SAR ADC algorithm with redundancy. - Tomohiko Ogawa; Haruo Kobayashi 001; Masao Hotta; Yosuke Takahashi; Hao San; Nobukazu Takai (APCCAS, 2008)

Novel Architecture of Feedforward Second-Order Multibit Delta-Sigma-AD Modulator. - Hao San; Hajime Konagaya; Feng Xu; Atsushi Motozawa; Haruo Kobayashi 001; Kazumasa Ando; Hiroshi Yoshida; Chieto Murayama; Kanichi Miyazawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Cross-Noise-Coupled Architecture of Complex Bandpass DeltaSigmaAD Modulator. - Hao San; Haruo Kobayashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Non-binary SAR ADC with digital error correction for low power applications. - Tomohiko Ogawa; Tatsuji Matsuura; Haruo Kobayashi 001; Nobukazu Takai; Masao Hotta; Hao San; Akira Abe; Katsuyoshi Yagi; Toshihiko Mori (APCCAS, 2010)

SAR ADC Algorithm with Redundancy and Digital Error Correction. - Tomohiko Ogawa; Haruo Kobayashi 001; Yosuke Takahashi; Nobukazu Takai; Masao Hotta; Hao San; Tatsuji Matsuura; Akira Abe; Katsuyoshi Yagi; Toshihiko Mori (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Noise-Coupled Image Rejection Architecture of Complex Bandpass DeltaSigmaAD Modulator. - Hao San; Haruo Kobayashi 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Rigorous analysis of quantization error of an A/D converter based on β-map. - Takaki Makino; Yukiko Iwata; Yutaka Jitsumatsu; Masao Hotta; Hao San; Kazuyuki Aihara (ISCAS, 2013)

Non-binary Pipeline Analog-to-Digital Converter Based on β-Expansion. - Hao San; Tomonari Kato; Tsubasa Maruyama; Kazuyuki Aihara; Masao Hotta (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Robust Cyclic ADC Architecture Based on β-Expansion. - Rie Suzuki; Tsubasa Maruyama; Hao San; Kazuyuki Aihara; Masao Hotta (IEICE Trans. Electron., 2013)

An area-efficient 12-bit 1.25MS/s radix-value self-estimated non-binary ADC with relaxed requirements on analog components. - Hao San; Rompei Sugawara; Masao Hotta; Tatsuji Matsuura; Kazuyuki Aihara (CICC, 2014)

Experimental Implementation of Non-binary Cyclic ADCs with Radix Value Estimation Algorithm. - Rompei Sugawara; Hao San; Kazuyuki Aihara; Masao Hotta (IEICE Trans. Electron., 2014)

A 10-bit 10Ms/s pipeline cyclic ADC based on β-expansion. - Yuta Mishima; Toshiki Yamada; Asato Uchiyama; Tatsuji Matsuura; Hao San; Masao Hotta (ISPACS, 2015)

A low-distortion delta-sigma modulator with ring amplifier and passive adder embedded SAR quantizer. - Chunhui Pan; Hao San (ISPACS, 2015)

Leakage current compensation technique of ESD protection circuit for CMOS operational amplifier. - Koken Chin; Hao San; Atsushi Kitajima; Yoshiaki Arai; Jun Yamashita; Hisashi Ito (ISPACS, 2016)

A 2nd-order Delta Sigma AD modulator using dynamic amplifier and dynamic SAR quantizer. - Chunhui Pan; Hao San; Tsugumichi Shibata (ISPACS, 2016)

Non-binary cyclic ADC with correlated level shifting technique. - Hiroyuki Tsuchiya; Asato Uchiyama; Yuta Misima; Yuki Watanabe; Tatsuji Matsuura; Hao San; Masao Hotta (ASP-DAC, 2017)

A 14bit 80kSPS non-binary cyclic ADC without high accuracy analog components. - Yuki Watanabe; Hayato Narita; Hiroyuki Tsuchiya; Tatsuji Matsuura; Hao San; Masao Hotta (ASP-DAC, 2017)

A 12-Bit 3.3MS/S pipeline cyclic ADC with correlated level shifting technique. - Koken Chin; Yuta Mishima; Yuki Watanabe; Hiroyuki Tsuchiya; Hao San; Tatsuji Matsuura; Masao Hotta (ISPACS, 2017)

The design of a 14-bit 400kSPS non-binary pipeline cyclic ADC. - Hiroyuki Tsuchiya; Yuki Watanabe; Koken Chin; Hao San; Tatsuji Matsuura; Masao Hotta (ISPACS, 2017)

Experimental results of reconfigurable non-binary cyclic ADC. - Yuki Watanabe; Koken Chin; Hiroyuki Tsuchiya; Hao San; Tatsuji Matsuura; Masao Hotta (ISPACS, 2017)

Non-binary cyclic and binary SAR hybrid ADC. - Kota Inoue; Tatsuji Matsuura; Akira Hyogo; Hao San (MIXDES, 2017)

A 2nd-order ΔΣAD modulator using ring amplifier and SAR quantizer with simplified operation mode. - Chunhui Pan; Hao San; Tsugumichi Shibata (MIXDES, 2017)

A 12-bit 1.25MS/s Area-Efficient Radix-Value Self-Estimated Non-Binary Cyclic ADC with Relaxed Requirements on Analog Components. - Hao San; Rompei Sugawara; Masao Hotta; Tatsuji Matsuura; Kazuyuki Aihara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A 6th-Order Complex Bandpass ΔΣ AD Modulator Using Dynamic Amplifier and Noise Coupling SAR Quantizer. - Chunhui Pan; Hao San (ISPACS, 2018)

A 720µW 77.93dB SNDR ΔΣ AD Modulator Using Dynamic Analog Components With Simplified Operation Phase. - Chunhui Pan; Hao San; Tsugumichi Shibata (ISPACS, 2018)

A 2nd-Order ΔΣAD Modulator Using Dynamic Analog Components with Simplified Operation Phase. - Chunhui Pan; Hao San (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

A Noise Coupled ΔΣAD Modulator Using Passive Adder Embedded Noise Shaping SAR Quantizer. - Chunhui Pan; Hao San (IEICE Trans. Electron., 2018)

Analog / Mixed-Signal / RF Circuits for Complex Signal Processing. - Haruo Kobayashi 001; Nene Kushita; Minh Tri Tran 001; Koji Asami; Hao San; Anna Kuwana; Akemi Hatta (ASICON, 2019)

A 0.8V 14bit 62.5kSPS non-binary cyclic ADC using SOTB CMOS technology. - Shuichiro Yamada; Toshiki Ohtsu; Minami Sasaki; Hao San; Tatsuji Matsuura; Masao Hotta (ISPACS, 2019)

Experimental implementation of delta sigma AD modulator using dynamic analog components with simplified operation phase. - Chunhui Pan; Hao San (IEICE Electron. Express, 2019)

A 6th-Order Quadrature Bandpass Delta Sigma AD Modulator Using Dynamic Amplifier and Noise Coupling SAR Quantizer. - Chunhui Pan; Hao San (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

Foreword. - Hao San (IEICE Trans. Electron., 2020)

Linearity Compensation for Conversion Error in Non-binary and Binary Hybrid ADC. - Yuanchi Chen; Hao San (ISPACS, 2021)

A 0.8V 14bit 294kSPS non-binary cyclic ADC in 65nm SOTB CMOS technology. - Eiki Kayama; Kenta Mori; Taichi Maebou; Yuanchi Chen; Hao San; Tatsuji Matsuura; Masao Hotta (ISPACS, 2021)

A 0.7V 14bit Hybrid ADC in 65nm SOTB CMOS. - Taichi Maebou; Yuanchi Chen; Eiki Kayama; Kenta Mori; Hao San; Tatsuji Matsuura; Masao Hotta (ISPACS, 2021)

A Low-voltage Non-binary Cyclic ADC using Fully Differential Ring Amplifier. - Kenta Mori; Eiki Kayama; Taichi Maebou; Yuanchi Chen; Hao San; Tatsuji Matsuura; Masao Hotta (ISPACS, 2021)

A Study on the Efficient Design of Adders Using Adiabatic Quantum-Flux-Parametron Circuits. - Tomoharu Yamauchi; Hao San; Nobuyuki Yoshikawa; Olivia Chen (GCCE, 2022)

Thermal Noise Analysis of Ring Amplifier in Cyclic Analog-to-Digital Converter. - Eiki Kayama; Kenta Mori; Taichi Maebou; Yuanchi Chen; Hao San; Tatsuji Matsuura; Masao Hotta (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2023)

Asynchronous SAR ADC with Parallel Comparators Inspired by Hopfield Network. - Keita Noda; Hao San; Xueyan Bai; Shogo Katayama; Dan Yao; Anna Kuwana; Zifei Xu; Haruo Kobayashi 001 (ISPACS, 2024)