Hao Wang

Affiliations:
  • University of California, San Diego, CA. USA


According to our database1, Hao Wang authored at least 16 papers between 2006 and 2014.

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Bibliography

2014
Reservation-Based Packet Bufferswith Deterministic Packet Departures.
IEEE Trans. Parallel Distributed Syst., 2014

2013
Robust Statistics Counter Arrays with Interleaved Memories.
IEEE Trans. Parallel Distributed Syst., 2013

Per-Flow Queue Management with Succinct Priority Indexing Structures for High Speed Packet Scheduling.
IEEE Trans. Parallel Distributed Syst., 2013

2012
DRAM-Based Statistics Counter Array Architecture With Performance Guarantee.
IEEE/ACM Trans. Netw., 2012

Robust Pipelined Memory System with Worst Case Performance Guarantee for Network Processing.
IEEE Trans. Computers, 2012

2011
Designing network traffic managers with throughput, fairness, and worst-case performance guarantees.
PhD thesis, 2011

Designing efficient codes for synchronization error channels.
Proceedings of the 19th International Workshop on Quality of Service, 2011

Per-flow Queue Scheduling with Pipelined Counting Priority Index.
Proceedings of the IEEE 19th Annual Symposium on High Performance Interconnects, 2011

2010
Design and Analysis of a Robust Pipelined Memory System.
Proceedings of the INFOCOM 2010. 29th IEEE International Conference on Computer Communications, 2010

Block-based packet buffer with deterministic packet departures.
Proceedings of the 11th IEEE International Conference on High Performance Switching and Routing, 2010

2009
A randomized interleaved DRAM architecture for the maintenance of exact statistics counters.
SIGMETRICS Perform. Evaluation Rev., 2009

Succinct priority indexing structures for the management of large priority queues.
Proceedings of the 17th International Workshop on Quality of Service, 2009

Design and performance analysis of a DRAM-based statistics counter array architecture.
Proceedings of the 2009 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2009

A block-based reservation architecture for the implementation of large packet buffers.
Proceedings of the 2009 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2009

2007
Pipelined van Emde Boas Tree: Algorithms, Analysis, and Applications.
Proceedings of the INFOCOM 2007. 26th IEEE International Conference on Computer Communications, 2007

2006
On the Efficient Implementation of Pipelined Heaps for Network Processing.
Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006


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