On the Efficient Implementation of Pipelined Heaps for Network Processing. - Hao Wang 006; Bill Lin 001 (GLOBECOM, 2006)

Pipelined van Emde Boas Tree: Algorithms, Analysis, and Applications. - Hao Wang 006; Bill Lin 001 (INFOCOM, 2007)

A block-based reservation architecture for the implementation of large packet buffers. - Hao Wang 006; Bill Lin 001 (ANCS, 2009)

Design and performance analysis of a DRAM-based statistics counter array architecture. - Haiquan (Chuck) Zhao; Hao Wang 006; Bill Lin 001; Jun (Jim) Xu (ANCS, 2009)

Succinct priority indexing structures for the management of large priority queues. - Hao Wang 006; Bill Lin 001 (IWQoS, 2009)

A randomized interleaved DRAM architecture for the maintenance of exact statistics counters. - Bill Lin 001; Jun (Jim) Xu; Nan Hua; Hao Wang 006; Haiquan (Chuck) Zhao (SIGMETRICS Perform. Evaluation Rev., 2009)

Block-based packet buffer with deterministic packet departures. - Hao Wang 006; Bill Lin 001 (HPSR, 2010)

Design and Analysis of a Robust Pipelined Memory System. - Hao Wang 006; Haiquan (Chuck) Zhao; Bill Lin 001; Jun (Jim) Xu (INFOCOM, 2010)

Per-flow Queue Scheduling with Pipelined Counting Priority Index. - Hao Wang 006; Bill Lin 001 (Hot Interconnects, 2011)

Designing efficient codes for synchronization error channels. - Hao Wang 006; Bill Lin 001 (IWQoS, 2011)

Designing network traffic managers with throughput, fairness, and worst-case performance guarantees. - Hao Wang 006 (2011)

Robust Pipelined Memory System with Worst Case Performance Guarantee for Network Processing. - Hao Wang 006; Haiquan (Chuck) Zhao; Bill Lin 001; Jun (Jim) Xu (IEEE Trans. Computers, 2012)

DRAM-Based Statistics Counter Array Architecture With Performance Guarantee. - Hao Wang 006; Haiquan (Chuck) Zhao; Bill Lin 001; Jun (Jim) Xu (IEEE/ACM Trans. Netw., 2012)

Per-Flow Queue Management with Succinct Priority Indexing Structures for High Speed Packet Scheduling. - Hao Wang 006; Bill Lin 001 (IEEE Trans. Parallel Distributed Syst., 2013)

Robust Statistics Counter Arrays with Interleaved Memories. - Hao Wang 006; Bill Lin 001; Jun (Jim) Xu (IEEE Trans. Parallel Distributed Syst., 2013)

Reservation-Based Packet Bufferswith Deterministic Packet Departures. - Hao Wang 006; Bill Lin 001 (IEEE Trans. Parallel Distributed Syst., 2014)