A 40Gb/s TX and RX chip set in 65nm CMOS. - Ming-Shuan Chen; Yu-Nan Shih; Chen-Lun Lin; Hao-Wei Hung; Jri Lee (ISSCC, 2011)

A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology. - Ming-Shuan Chen; Yu-Nan Shih; Chen-Lun Lin; Hao-Wei Hung; Jri Lee (IEEE J. Solid State Circuits, 2012)

100Gb/s ethernet chipsets in 65nm CMOS technology. - Jhih-Yu Jiang; Ping-Chuan Chiang; Hao-Wei Hung; Chen-Lun Lin; Ty Yoon; Jri Lee (ISSCC, 2013)

Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester chipsets in 65-nm CMOS technology. - Guan-Sing Chen; Chin-Yang Wu; Chen-Lun Lin; Hao-Wei Hung; Jri Lee (A-SSCC, 2014)

2.3 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS. - Ping-Chuan Chiang; Hao-Wei Hung; Hsiang-Yun Chu; Guan-Sing Chen; Jri Lee (ISSCC, 2014)

4×25 Gb/s Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Technology. - Ping-Chuan Chiang; Jhih-Yu Jiang; Hao-Wei Hung; Chin-Yang Wu; Gaun-Sing Chen; Jri Lee (IEEE J. Solid State Circuits, 2015)

6.1 A 112Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR-ADC and Inverter-Based RX Analog Front-End in 7nm FinFET. - Jay Im; Kevin Zheng; Adam Chou; Lei Zhou; Jae Wook Kim; Stanley Chen; Yipeng Wang 003; Hao-Wei Hung; Kee Hian Tan; Winson Lin; Arianne Roldan; Declan Carey; et al. (ISSCC, 2020)

A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET. - Jay Im; Kevin Zheng; Chuen-Huei Adam Chou; Lei Zhou; Jae Wook Kim; Stanley Chen; Yipeng Wang 003; Hao-Wei Hung; Kee Hian Tan; Winson Lin; Arianne Roldan; Declan Carey; et al. (IEEE J. Solid State Circuits, 2021)