Testing retention flip-flops in power-gated designs. - Hao-Wen Hsu; Shih-Hua Kuo; Wen-Hsiang Chang; Shi-Hao Chen; Ming-Tung Chang; Mango Chia-Tso Chao (VTS, 2013)

25 Gb/s NRZ and 50 Gb/s PAM-4 Transimpedance Amplifier with Active Feedback and Equalization in 90 nm CMOS Technology. - Hao-Wen Hsu; Chih-Chen Peng; Jau-Ji Jou; Tien-Tsorng Shih; Yaw-Dung Wu; Shao-I Chu; Chih-Yuan Lien; Bing-Hong Liu (ICETE (1), 2019)

A 40-Gb/s NRZ Inductorless Transimpedance Amplifier in a 0.18-μm SiGe BiCMOS Technology. - Hao-Wen Hsu; Xuan-Yi Ye; Jau-Ji Jou; Tien-Tsorng Shih (ISPACS, 2021)

A 5nm 5.7GHz@1.0V and 1.3GHz@0.5V 4kb Standard-Cell- Based Two-Port Register File with a 16T Bitcell with No Half-Selection Issue. - Hidehiro Fujiwara; Yi-Hsin Nien; Chih-Yu Lin; Hsien-Yu Pan; Hao-Wen Hsu; Shin-Rung Wu; Yao-Yi Liu; Yen-Huei Chen; Hung-Jen Liao; Jonathan Chang (ISSCC, 2021)

32-Gb/s NRZ and 40-Gb/s PAM-4 Transimpedance Amplifier Paralleling with a Differentiator for Bandwidth Enhancement in 90-nm CMOS Technology. - Jau-Ji Jou; Tien-Tsorng Shih; Hao-Wen Hsu (Circuits Syst. Signal Process., 2022)