Understanding the regenerative comparator circuit. - Asad A. Abidi; Hao Xu 005 (CICC, 2014)

3.6 A noise-cancelling receiver with enhanced resilience to harmonic blockers. - David Murphy; Hooman Darabi; Hao Xu 005 (ISSCC, 2014)

A Noise-Cancelling Receiver Resilient to Large Harmonic Blockers. - David Murphy; Hooman Darabi; Hao Xu 005 (IEEE J. Solid State Circuits, 2015)

Design Methodology for Phase-Locked Loops Using Binary (Bang-Bang) Phase Detectors. - Hao Xu 005; Asad A. Abidi (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A Calibration-Free Triple-Loop Bang-Bang PLL Achieving 131fsrms Jitter and-70dBc Fractional Spurs. - Dihang Yang; Asad A. Abidi; Hooman Darabi; Hao Xu 005; David Murphy; Hao Wu 026; Zhaowen Wang (ISSCC, 2019)

Analysis and Design of Regenerative Comparators for Low Offset and Noise. - Hao Xu 005; Asad A. Abidi (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Tutorial on Systematic Design of CMOS A/D Converters: Illustrated by a 10 b, 500 MS/s SAR ADC with 2 GHz RBW. - Tetsuya Iizuka; Hao Xu 005; Asad A. Abidi (ESSCIRC, 2021)

A 6-18GHz Low-Noise Amplifier Using Noise Canceling Technique in 130-nm CMOS PD-SOI. - Jialong Xue; Tenghao Zou; Hao Xu 005; Tingting Han; Mi Tian; Weiqiang Zhu; Zhijian Li; Na Yan (ICTA, 2022)

A High Speed, Low Power and Low Phase Noise Divider for Wideband Application. - Xinyi Lin; Hao Xu 005; Dejian Li; Na Yan (ASICON, 2023)

An ADPLL Design Model Based on LoRa IoT Application. - Yiyun Mao; Haoyuan Gao; Dejian Li; Hao Xu 005; Na Yan (ASICON, 2023)

A Vernier Time-to-Digital Converter with 1.5ps Resolution for an All-Digital Phase Locked Loop in 28nm CMOS. - Peifang Wu; Yan Liu; Xi Feng; Hao Xu 005; Na Yan (ASICON, 2023)

Analysis and Modeling of Non-ideal Effects in SAR ADC. - Yaxin Zeng; Hao Xu 005; Xi Feng; Na Yan (ASICON, 2023)

A 26-30GHz Digitally-Controlled Variable Gain Power Amplifier with Phase Compensation and Third Order Nonlinearity Cancellation Technique. - Haoqi Qin; Junjie Gu; Hao Xu 005; Weitian Liu; Kefeng Han; Rui Yin; Zongming Duan; Hao Gao 001; Na Yan (A-SSCC, 2023)

Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9-14.3-GHz 85-fs-rms Jitter PLL. - Yizhuo Wang; Jiahe Shi; Hao Xu 005; Shujiang Ji; Yiyun Mao; Tenghao Zou; Jun Tao 001; Hao Min; Na Yan (IEEE J. Solid State Circuits, 2023)

A 6-12 GHz Wideband Low-Noise Amplifier With 0.8-1.5 dB NF and ±0.75 dB Ripple Enabled by the Capacitor Assisting Triple-Winding Transformer. - Tenghao Zou; Hao Xu 005; Yizhuo Wang; Weitian Liu; Tingting Han; Mi Tian; Weiqiang Zhu; Na Yan (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier. - Wenning Jiang; Yan Zhu 001; Chixiao Chen; Hao Xu 005; Qi Liu 010; Ming Liu 022; Rui Paulo Martins; Chi-Hang Chan (IEEE J. Solid State Circuits, 2023)

An 8-14GHz 180fs-rms DTC-Less Fractional ADPLL with ADC-Based Direct Phase Digitization in 40nm CMOS. - Yizhuo Wang; Hao Xu 005; Guoyu Li; Shuai Liu; Yan Liu; Rui Yin; Hui Pan; Na Yan (CICC, 2024)

5.1 A 5-to-16GHz Reconfigurable Quadrature Receiver with 50% Duty-Cycle LO and IQ-Leakage Suppression. - Hao Xu 005; Junyan Bi; Tenghao Zou; Weitao He; Yaxin Zeng; Junjie Gu; Ziyang Jiao; Shubin Liu; Zhangming Zhu; Na Yan (ISSCC, 2024)

A 10-bit 563-fs Step Constant-Slope Digital-to-Time Converter in 40-nm CMOS With Nonlinearity Cancellation and Range Extension Techniques. - Yan Liu; Haoyuan Gao; Hao Xu 005; Ping Lu; Na Yan (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Analysis and Design of a Sub-Sampling PLL of Low Phase Noise and Low Reference Spur. - Hao Xu 005; Shujiang Ji; Yizhuo Wang; Xinyi Lin; Hao Min; Na Yan (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

19.11 A 13GHz Charge-Pump PLL Achieving 15.8fsrms Integrated Jitter and -98.5dBc Reference Spur. - Depeng Sun; Feng Bu; Qixian Ye; Shijie Li; Yuan Gao; Bowen Wang; Hao Xu 005; Na Yan; Shubin Liu; Zhangming Zhu (ISSCC, 2025)

A 12-bit 2GS/s current-steering DAC with 27 mW power consumption in 28 nm CMOS. - Beiqi Duan; Junyan Bi; Hao Xu 005; Guoyu Li; Yechen Tian; Na Yan (Microelectron. J., 2025)

A 2 MHz-BW 80.6 dB-SNDR 95.9 dB-SFDR 2nd-order noise-shaping SAR using open-loop Gm-R amplifier. - Hao Xu 005; Congyang Sun; Shuai Liu; Guoyu Li; Yechen Tian; Na Yan (Microelectron. J., 2025)

Design and Analysis of a 26-32-GHz 6-bit Passive Vector Modulation Phase Shifter for CMOS Bidirectional Transceiver. - Yechen Tian; Yutong Zhang; Junjie Gu; Hao Xu 005; Weitian Liu; Rui Yin; Zongming Duan; Hao Gao 001; Na Yan (IEEE Trans. Very Large Scale Integr. Syst., 2025)

An All-Digital Spread-Spectrum Clock Generator With Feedforward Gain Calibration for LPWAN Chirp Transmission System. - Yiyun Mao; Haoyuan Gao; Jin Shao; Xinyi Lin; Peifang Wu; Ping Lu; Hao Xu 005; Na Yan (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A 25-31-GHz Compact True Power Detector With >33-dB Dynamic Range and Intrinsic Phase Offset Compensation in 40-nm Bulk CMOS. - Haoqi Qin; Junjie Gu; Hao Xu 005; Zhiwei Xu 003; Pengcheng Jia; Na Yan (IEEE J. Solid State Circuits, 2025)

Systematic Design of a 3.5 GS/s 11-bit Time-Interleaved SAR ADC in 28 nm CMOS Achieving 54 dB SNDR at Nyquist Frequency. - Shuai Liu; Yechen Tian; Congyang Sun; Guoyu Li; Hao Xu 005; Na Yan (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A 5-18-GHz Reconfigurable Quadrature Receiver With Enhanced I-Q Isolation and 100-500-MHz Baseband Bandwidth. - Junyan Bi; Hao Xu 005; Tenghao Zou; Yaxin Zeng; Yechen Tian; Weitao He; Junjie Gu; Ziyang Jiao; Shubin Liu; Zhangming Zhu; Na Yan (IEEE J. Solid State Circuits, 2025)

A 0.2-19GHz Zero-IF Reconfigurable Quadrature Transmitter With T-Coil Matching Network. - An Sun; Yaxin Zeng; Haoqi Qin; Hao Xu 005; Rui Yin; Xiaoliang Shen; Lifeng Bian; Na Yan (IEEE Trans. Circuits Syst. II Express Briefs, 2025)