Hao Yu

According to our database1, Hao Yu authored at least 158 papers between 2003 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
DEEPEYE: A Deeply Tensor-Compressed Neural Network for Video Comprehension on Terminal Devices.
ACM Trans. Embed. Comput. Syst., 2020

S3-Net: A Fast and Lightweight Video Scene Understanding Network by Single-shot Segmentation.
CoRR, 2020

HOTCAKE: Higher Order Tucker Articulated Kernels for Deeper CNN Compression.
CoRR, 2020

Energy-Efficient Machine Learning Accelerator for Binary Neural Networks.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

An Anomaly Comprehension Neural Network for Surveillance Videos on Terminal Devices.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
LTNN: A Layerwise Tensorized Compression of Multilayer Neural Network.
IEEE Trans. Neural Networks Learn. Syst., 2019

A 34-FPS 698-GOP/s/W Binarized Deep Neural Network-Based Natural Scene Text Interpretation Accelerator for Mobile Edge Computing.
IEEE Trans. Ind. Electron., 2019

A 5-10-Gb/s 12.5-mW Source Synchronous I/O Interface With 3-D Flip Chip Package.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A large-scale in-memory computing for deep neural network with trained quantization.
Integr., 2019

A 307-fps 351.7-GOPs/W Deep Learning FPGA Accelerator for Real-Time Scene Text Recognition.
Proceedings of the International Conference on Field-Programmable Technology, 2019

DEEPEYE: A Deeply Tensor-Compressed Neural Network Hardware Accelerator: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019

Fast video facial expression recognition by deeply tensor-compressed LSTM neural network on mobile device.
Proceedings of the 4th ACM/IEEE Symposium on Edge Computing, 2019

ANT-UNet: Accurate and Noise-Tolerant Segmentation for Pathology Image Processing.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

A Low-Power High-Throughput In-Memory CMOS-ReRAM Accelerator for Large-Scale Deep Residual Neural Networks.
Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018
Distributed Machine Learning on Smart-Gateway Network toward Real-Time Smart-Grid Energy Management with Behavior Cognition.
ACM Trans. Design Autom. Electr. Syst., 2018

A High-Sensitivity Potentiometric 65-nm CMOS ISFET Sensor for Rapid E. coli Screening.
IEEE Trans. Biomed. Circuits Syst., 2018

A GPU-Outperforming FPGA Accelerator Architecture for Binary Convolutional Neural Networks.
ACM J. Emerg. Technol. Comput. Syst., 2018

Q-Learning-Based Voltage-Swing Tuning and Compensation for 2.5-D Memory-Logic Integration.
IEEE Des. Test, 2018

DEEPEYE: A Compact and Accurate Video Comprehension at Terminal Devices Compressed with Quantization and Tensorization.
CoRR, 2018

Symbolic Circuit Reduction for Multistage Amplifier Macromodeling.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A Multiagent Minority-Game-Based Demand-Response Management of Smart Buildings Toward Peak Load Reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Data-Driven Sampling Matrix Boolean Optimization for Energy-Efficient Biomedical Signal Acquisition by Compressive Sensing.
IEEE Trans. Biomed. Circuits Syst., 2017

A Microfluidic Cytometer for Complete Blood Count With a 3.2-Megapixel, 1.1- μm-Pitch Super-Resolution Image Sensor in 65-nm BSI CMOS.
IEEE Trans. Biomed. Circuits Syst., 2017

A 23-mW Face Recognition Processor with Mostly-Read 5T Memory in 40-nm CMOS.
IEEE J. Solid State Circuits, 2017

Distributed In-Memory Computing on Binary RRAM Crossbar.
ACM J. Emerg. Technol. Comput. Syst., 2017

LTNN: An energy-efficient machine learning accelerator on 3D CMOS-RRAM for layer-wise tensorized neural network.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Developing a web-based symbolic circuit analysis tool for learning and design aid.
Proceedings of the 14th International Conference on Synthesis, 2017

An energy-efficient and high-throughput bitwise CNN on sneak-path-free digital ReRAM crossbar.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

NucleiNet: A convolutional encoder-decoder network for bio-image denoising.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017

A fast online sequential learning accelerator for IoT network intrusion detection: work-in-progress.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

An efficient 4-way-combined 291 GHz signal source with 1.75 mW peak output power in 65 nm CMOS.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
Non-Volatile In-Memory Computing by Spintronics
Synthesis Lectures on Emerging Engineering Technologies, Morgan & Claypool Publishers, 2016

DW-AES: A Domain-Wall Nanowire-Based AES for High Throughput and Energy-Efficient Data Encryption in Non-Volatile Memory.
IEEE Trans. Inf. Forensics Secur., 2016

A Zonotoped Macromodeling for Eye-Diagram Verification of High-Speed I/O Links With Jitter and Parameter Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A Q-Learning Based Self-Adaptive I/O Communication for 2.5D Integrated Many-Core Microprocessor and Memory.
IEEE Trans. Computers, 2016

Machine Learning Based Single-Frame Super-Resolution Processing for Lensless Blood Cell Counting.
Sensors, 2016

Editorial.
J. Circuits Syst. Comput., 2016

Distributed machine learning based smart-grid energy management with occupant cognition.
Proceedings of the 2016 IEEE International Conference on Smart Grid Communications, 2016

Racetrack memory-based encoder/decoder for low-power interconnect architectures.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

A memristor network with coupled oscillator and crossbar towards L2-norm based machine learning.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

A Compressive-sensing based Testing Vehicle for 3D TSV Pre-bond and Post-bond Testing Data.
Proceedings of the 2016 on International Symposium on Physical Design, 2016

Low-power and real-time computer vision on-chip.
Proceedings of the International SoC Design Conference, 2016

On-line machine learning accelerator on digital RRAM-crossbar.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Lab-on-CMOS: A multi-modal CMOS sensor platform towards personalized DNA sequencing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Distributed-neuron-network based machine learning on smart-gateway network towards real-time indoor data analytics.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A convolutional neural network based single-frame super-resolution for lensless blood cell counting.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

A 3D multi-layer CMOS-RRAM accelerator for neural network.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015
A GPU-Accelerated Parallel Shooting Algorithm for Analysis of Radio Frequency and Microwave Integrated Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2015

3D Many-Core Microprocessor Power Management by Space-Time Multiplexing Based Demand-Supply Matching.
IEEE Trans. Computers, 2015

A Dual-Mode Large-Arrayed CMOS ISFET Sensor for Accurate and High-Throughput pH Sensing in Biomedical Diagnosis.
IEEE Trans. Biomed. Eng., 2015

An Ultra-Low Power CMOS Image Sensor with On-Chip Energy Harvesting and Power Management Capability.
Sensors, 2015

A robust recognition error recovery for micro-flow cytometer by machine-learning enhanced single-frame super-resolution processing.
Integr., 2015

A 2.5-D Memory-Logic Integration With Data-Pattern-Aware Memory Controller.
IEEE Des. Test, 2015

A Single-Frame Superresolution Algorithm for Lab-on-a-Chip Lensless Microfluidic Imaging.
IEEE Des. Test, 2015

A 23mW face recognition accelerator in 40nm CMOS with mostly-read 5T memory.
Proceedings of the Symposium on VLSI Circuits, 2015

Smart I/Os: a data-pattern aware 2.5D interconnect with space-time multiplexing.
Proceedings of the 2015 ACM/IEEE International Workshop on System Level Interconnect Prediction, 2015

Optimizing Boolean embedding matrix for compressive sensing in RRAM crossbar.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

An energy efficient and low cross-talk CMOS sub-THz I/O with surface-wave modulator and interconnect.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

A body-biasing of readout circuit for STT-RAM with improved thermal reliability.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 16-channel 24-V 1.8-mA power efficiency enhanced neural/muscular stimulator with exponentially decaying stimulation current.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

An energy-efficient non-volatile in-memory accelerator for sparse-representation based face recognition.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A scalable and reconfigurable 2.5D integrated multicore processor on silicon interposer.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

A 201 mV/pH, 375 fps and 512×576 CMOS ISFET sensor in 65nm CMOS technology.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

A 64×64 1200fps dual-mode CMOS ion-image sensor for accurate DNA sequencing.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

A CMOS THz-sensing system towards label-free DNA sequencing.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
Nonvolatile CBRAM-Crossbar-Based 3-D-Integrated Hybrid Memory for Data Retention.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Design and Analysis of Wide Frequency-Tuning-Range CMOS 60 GHz VCO by Switching Inductor Loaded Transformer.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Reachability-Based Robustness Verification and Optimization of SRAM Dynamic Stability Under Process Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Variability-Aware Parametric Yield Estimation for Analog/Mixed-Signal Circuits: Concepts, Algorithms, and Challenges.
IEEE Des. Test, 2014

A 64×64 1200fps CMOS ion-image sensor with suppressed fixed-pattern-noise for accurate high-throughput DNA sequencing.
Proceedings of the Symposium on VLSI Circuits, 2014

An energy-efficient 2.5D through-silicon interposer I/O with self-adaptive adjustment of output-voltage swing.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

An overview of new design techniques for high performance CMOS millimeter-wave circuits.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Reinforcement learning based self-adaptive voltage-swing adjustment of 2.5D I/Os for many-core microprocessor and memory communication.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

A zonotoped macromodeling for reachability verification of eye-diagram in high-speed I/O links with jitter.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

A high-sensitivity 135GHz millimeter-wave imager by differential transmission-line loaded split-ring-resonator in 65nm CMOS.
Proceedings of the 44th European Solid State Device Research Conference, 2014

A 131.5GHz, -84dBm sensitivity super-regenerative receiver by zero-phase-shifter coupled oscillator network in 65nm CMOS.
Proceedings of the ESSCIRC 2014, 2014

A thermal resilient integration of many-core microprocessors and main memory by 2.5D TSI I/Os.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Energy efficient in-memory AES encryption based on nonvolatile domain-wall nanowire.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Zonotope-based nonlinear model order reduction for fast performance bound analysis of analog circuits with multiple-interval-valued parameter variations.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A 239-281GHz Sub-THz imager with 100MHz resolution by CMOS direct-conversion receiver with on-chip circular-polarized SIW antenna.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

A 127-140GHz injection-locked signal source with 3.5mW peak output power by zero-phase coupled oscillator network in 65nm CMOS.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

Energy efficient in-memory machine learning for data intensive image-processing by non-volatile domain-wall memory.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

A robustness optimization of SRAM dynamic stability by sensitivity-based reachability analysis.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Design Exploration of Emerging Nano-scale Non-volatile Memory.
Springer, ISBN: 978-1-4939-0550-8, 2014

2013
A 96-GHz Oscillator by High-Q Differential Transmission Line loaded with Complementary Split-Ring Resonator in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

A Dividerless PLL With Low Power and Low Reference Spur by Aperture-Phase Detector and Phase-to-Analog Converter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Stochastic Behavioral Modeling and Analysis for Analog/Mixed-Signal Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Reliable 3-D Clock-Tree Synthesis Considering Nonlinear Capacitive TSV Model With Electrical-Thermal-Mechanical Coupling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

An efficient channel clustering and flow rate allocation algorithm for non-uniform microfluidic cooling of 3D integrated circuits.
Integr., 2013

SPECO: Stochastic Perturbation based Clock tree Optimization considering temperature uncertainty.
Integr., 2013

Design and Analysis of CMOS-Based Terahertz Integrated Circuits by Causal Fractional-Order RLGC Transmission Line Model.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2013

Exploiting Parallelism by Data Dependency Elimination: A Case Study of Circuit Simulation Algorithms.
IEEE Des. Test, 2013

On the futility of thermal through-silicon-vias.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

SRAM dynamic stability verification by reachability analysis with consideration of threshold voltage variation.
Proceedings of the International Symposium on Physical Design, 2013

An ultralow-power memory-based big-data computing platform by nonvolatile domain-wall nanowire devices.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

A 5-bit 1.25GS/s 4.7mW delay-based pipelined ADC in 65nm CMOS.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Cyber-physical management for heterogeneously integrated 3D thousand-core on-chip microprocessor.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A high-frequency transimpedance amplifier for CMOS integrated 2D CMUT array towards 3D ultrasound imaging.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013

3D reconfigurable power switch network for demand-supply matching between multi-output power converters and many-core microprocessors.
Proceedings of the Design, Automation and Test in Europe, 2013

Peak power reduction and workload balancing by space-time multiplexing based demand-supply matching for 3D thousand-core microprocessor.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

A 75.7GHz to 102GHz rotary-traveling-wave VCO by tunable composite right /left hand T-line.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

Stable backward reachability correction for PLL verification with consideration of environmental noise induced jitter.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Thermal-reliable 3D clock-tree synthesis considering nonlinear electrical-thermal-coupled TSV model.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Thermal simulator of 3D-IC with modeling of anisotropic TSV conductance and microchannel entrance effects.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

High-speed and low-power 2.5D I/O circuits for memory-logic-integration by through-silicon interposer.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
A Parallel and Incremental Extraction of Variational Capacitance With Stochastic Geometric Moments.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Design Exploration of Hybrid CMOS and Memristor Circuit by New Modified Nodal Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A Fast Non-Monte-Carlo Yield Analysis and Optimization by Stochastic Orthogonal Polynomials.
ACM Trans. Design Autom. Electr. Syst., 2012

Analysis and Modeling of Internal State Variables for Dynamic Effects of Nonvolatile Memory Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Fast timing analysis of clock networks considering environmental uncertainty.
Integr., 2012

Design exploration of ultra-low power non-volatile memory based on topological insulator.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Design of low power 3D hybrid memory by non-volatile CBRAM-crossbar with block-level data-retention.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Decentralized agent based re-clustering for task mapping of tera-scale network-on-chip system.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Distributed thermal-aware task scheduling for 3D Network-on-Chip.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Fair energy resource allocation by minority game algorithm for smart buildings.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A GPU-accelerated envelope-following method for switching power converter simulation.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Fast simulation of hybrid CMOS and STT-MTJ circuits with identified internal state variables.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

A 96×96 1V ultra-low power CMOS image sensor for biomedical application.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs.
Springer, ISBN: 978-1-4614-0787-4, 2012

2011
An EScheduler-Based Data Dependence Analysis and Task Scheduling for Parallel Circuit Simulation.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

Cyber-Physical Thermal Management of 3D Multi-Core Cache-Processor System with Microfluidic Cooling.
J. Low Power Electron., 2011

NEMS based thermal management for 3D many-core system.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Stochastic analog circuit behavior modeling by point estimation method.
Proceedings of the 2011 International Symposium on Physical Design, 2011

On the preconditioner of conjugate gradient method - A power grid simulation perspective.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Fast non-monte-carlo transient noise analysis for high-precision analog/RF circuits by stochastic orthogonal polynomials.
Proceedings of the 48th Design Automation Conference, 2011

A 2.1-GHz PLL with -80dBc/-74dBc reference spur based on aperture-phase detector and phase-to-analog converter.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

A structured parallel periodic Arnoldi shooting algorithm for RF-PSS analysis based on GPU platforms.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Design exploration of 3D stacked non-volatile memory by conductive bridge based crossbar.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010
Fast Analysis of a Large-Scale Inductive Interconnect by Block-Structure-Preserved Macromodeling.
IEEE Trans. Very Large Scale Integr. Syst., 2010

A new modified nodal analysis for nano-scale memristor circuit simulation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A robust periodic arnoldi shooting algorithm for efficient analysis of large-scale RF/MM ICs.
Proceedings of the 47th Design Automation Conference, 2010

QuickYield: an efficient global-search based parametric yield estimation with performance constraints.
Proceedings of the 47th Design Automation Conference, 2010

A fast analog mismatch analysis by an incremental and stochastic trajectory piecewise linear macromodel.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Real-time thermal management of 3D multi-core system with fine-grained cooling control.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity.
ACM Trans. Design Autom. Electr. Syst., 2009

Robust On-Chip Signaling by Staggered and Twisted Bundle.
IEEE Des. Test Comput., 2009

PiCAP: a parallel and incremental capacitance extraction considering stochastic process variation.
Proceedings of the 46th Design Automation Conference, 2009

Fast analysis of nontree-clock network considering environmental uncertainty by parameterized and incremental macromodeling.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Thermal Via Allocation for 3-D ICs Considering Temporally and Spatially Variant Thermal Power.
IEEE Trans. Very Large Scale Integr. Syst., 2008

2007
Circuit-simulated obstacle-aware Steiner routing.
ACM Trans. Design Autom. Electr. Syst., 2007

General Block Structure-Preserving Reduced Order Modeling of Linear Dynamic Circuits.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Minimal skew clock embedding considering time variant temperature gradient.
Proceedings of the 2007 International Symposium on Physical Design, 2007

Off-chip Decoupling Capacitor Allocation for Chip Package Co-Design.
Proceedings of the 44th Design Automation Conference, 2007

2006
Wideband passive multiport model order reduction and realization of RLCM circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

SAMSON: a generalized second-order arnoldi method for reducing multiple source linear network with susceptance.
Proceedings of the 2006 International Symposium on Physical Design, 2006

Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

A fast block structure preserving model order reduction for inverse inductance circuits.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Simultaneous power and thermal integrity driven via stapling in 3D ICs.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Fast analysis of structured power grid by triangularization based structure preserving model order reduction.
Proceedings of the 43rd Design Automation Conference, 2006

Circuit simulation based obstacle-aware Steiner routing.
Proceedings of the 43rd Design Automation Conference, 2006

2005
A provably passive and cost-efficient model for inductive interconnects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

A sparsified vector potential equivalent circuit model for massively coupled interconnects.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A wideband hierarchical circuit reduction for massively coupled interconnects.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2003
Vector potential equivalent circuit based on PEEC inversion.
Proceedings of the 40th Design Automation Conference, 2003


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