Hao Yu
Orcid: 0000-0001-8747-3203Affiliations:
- Southern University of Science and Technology, Shenzhen, China
- Nanyang Technological University, School of Electrical and Electronic Engineering, Singapore (former)
- Berkeley Design Automation, Santa Clara, CA, USA (former)
- University of California at Los Angeles, Department of Electrical Engineering, CA, USA (PhD 2007)
According to our database1,
Hao Yu
authored at least 221 papers
between 2003 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
IEEE Open J. Circuits Syst., 2024
APTQ: Attention-aware Post-Training Mixed-Precision Quantization for Large Language Models.
CoRR, 2024
2023
Novel Wideband Millimeter-Wave GaN Power Amplifier Design Using Transistors With Large Drain Capacitance and High Optimum Load Impedance.
IEEE Trans. Circuits Syst. II Express Briefs, December, 2023
An Integer-Only and Group-Vector Systolic Accelerator for Efficiently Mapping Vision Transformer on Edge.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
Reliability Exploration of System-on-Chip With Multi-Bit-Width Accelerator for Multi-Precision Deep Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023
A Low-Power Sparse Convolutional Neural Network Accelerator With Pre-Encoding Radix-4 Booth Multiplier.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023
TT-LCD: Tensorized-Transformer based Loop Closure Detection for Robotic Visual SLAM on Edge.
Proceedings of the International Conference on Advanced Robotics and Mechatronics, 2023
Multi-bit-width CNN Accelerator with Systolic-in-Systolic Dataflow and Single DSP Multiple Multiplication Scheme.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023
RankSearch: An Automatic Rank Search Towards Optimal Tensor Compression for Video LSTM Networks on Edge.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Agile Hardware and Software Co-Design for RISC-V-Based Multi-Precision Deep Learning Microprocessor.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
RISC-V based Fully-Parallel SRAM Computing-in-Memory Accelerator with High Hardware Utilization and Data Reuse Rate.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
A Fall Detection Network by 2D/3D Spatio-temporal Joint Models with Tensor Compression on Edge.
ACM Trans. Embed. Comput. Syst., November, 2022
A Configurable Floating-Point Multiple-Precision Processing Element for HPC and AI Converged Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2022
An Energy-Efficient Mixed-Bitwidth Systolic Accelerator for NAS-Optimized Deep Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2022
ACM Trans. Design Autom. Electr. Syst., 2022
A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
ACM J. Emerg. Technol. Comput. Syst., 2022
An Energy-Efficient Mixed-Bit CNN Accelerator With Column Parallel Readout for ReRAM-Based In-Memory Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
A 703.4-GOPs/W Binary SegNet Processor With Computing-Near-Memory Architecture for Road Detection.
IEEE Des. Test, 2022
FASSST: Fast Attention Based Single-Stage Segmentation Net for Real-Time Instance Segmentation.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2022
Proceedings of the International Conference on Advanced Robotics and Mechatronics , 2022
A High Throughput Multi-bit-width 3D Systolic Accelerator for NAS Optimized Deep Neural Networks on FPGA.
Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022
BaseFormer: Transformer based Base-Caller for Fast and Accurate Next Generation Sequencing.
Proceedings of the 44th Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2022
A Precision-Scalable Energy-Efficient Bit-Split-and-Combination Vector Systolic Accelerator for NAS-Optimized DNNs on Edge.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
An Energy-Efficient Bit-Split-and-Combination Systolic Accelerator for NAS-Based Multi-Precision Convolution Neural Networks.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
Hierarchical DNN with Heterogeneous Computing Enabled High-Performance DNA Sequencing.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
An Energy-Efficient Mixed-Bit ReRAM-based Computing-in-Memory CNN Accelerator with Fully Parallel Readout.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
A Low-Power Approximate Multiplier with Sign-Focus Compressor and Error Compensation.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
S3-Net: A Fast Scene Understanding Network by Single-Shot Segmentation for Autonomous Driving.
ACM Trans. Intell. Syst. Technol., 2021
Fast Video Facial Expression Recognition by a Deeply Tensor-Compressed LSTM Neural Network for Mobile Devices.
ACM Trans. Internet Things, 2021
TEANS: A Target Enhancement and Attenuated Nonmaximum Suppression Object Detector for Remote Sensing Images.
IEEE Geosci. Remote. Sens. Lett., 2021
Energy-Efficient and Error-Resilient Cognitive I/O for 3-D-Integrated Manycore Microprocessors.
IEEE Des. Test, 2021
S3-Net: A Fast and Lightweight Video Scene Understanding Network by Single-shot Segmentation.
Proceedings of the IEEE Winter Conference on Applications of Computer Vision, 2021
Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
A Reconfigurable Multiple-Precision Floating-Point Dot Product Unit for High-Performance Computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
A Video-based Fall Detection Network by Spatio-temporal Joint-point Model on Edge Devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Multiple-Precision Floating-Point Dot Product Unit for Efficient Convolution Computation.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
DEEPEYE: A Deeply Tensor-Compressed Neural Network for Video Comprehension on Terminal Devices.
ACM Trans. Embed. Comput. Syst., 2020
CoRR, 2020
Analog Integrated Circuits Based on Wafer-Level Two-Dimensional MoS<sub>2</sub> Materials With Physical and SPICE Model.
IEEE Access, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Design and Analysis of $D$ -Band On-Chip Modulator and Signal Source Based on Split-Ring Resonator.
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Neural Networks Learn. Syst., 2019
A 34-FPS 698-GOP/s/W Binarized Deep Neural Network-Based Natural Scene Text Interpretation Accelerator for Mobile Edge Computing.
IEEE Trans. Ind. Electron., 2019
IEEE Trans. Emerg. Top. Comput. Intell., 2019
IEEE Trans. Commun., 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Integr., 2019
A 307-fps 351.7-GOPs/W Deep Learning FPGA Accelerator for Real-Time Scene Text Recognition.
Proceedings of the International Conference on Field-Programmable Technology, 2019
DEEPEYE: A Deeply Tensor-Compressed Neural Network Hardware Accelerator: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019
Fast video facial expression recognition by deeply tensor-compressed LSTM neural network on mobile device.
Proceedings of the 4th ACM/IEEE Symposium on Edge Computing, 2019
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019
A Low-Power High-Throughput In-Memory CMOS-ReRAM Accelerator for Large-Scale Deep Residual Neural Networks.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
Distributed Machine Learning on Smart-Gateway Network toward Real-Time Smart-Grid Energy Management with Behavior Cognition.
ACM Trans. Design Autom. Electr. Syst., 2018
A High-Sensitivity Potentiometric 65-nm CMOS ISFET Sensor for Rapid E. coli Screening.
IEEE Trans. Biomed. Circuits Syst., 2018
A GPU-Outperforming FPGA Accelerator Architecture for Binary Convolutional Neural Networks.
ACM J. Emerg. Technol. Comput. Syst., 2018
Q-Learning-Based Voltage-Swing Tuning and Compensation for 2.5-D Memory-Logic Integration.
IEEE Des. Test, 2018
DEEPEYE: A Compact and Accurate Video Comprehension at Terminal Devices Compressed with Quantization and Tensorization.
CoRR, 2018
IEEE Access, 2018
D-Band Surface-Wave Modulator and Signal Source with 40 dB Extinction Ratio and 3.7mW Output Power in 65 nm CMOS.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018
SqueezedText: A Real-Time Scene Text Recognition by Binary Convolutional Encoder-Decoder Network.
Proceedings of the Thirty-Second AAAI Conference on Artificial Intelligence, 2018
2017
A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A Multiagent Minority-Game-Based Demand-Response Management of Smart Buildings Toward Peak Load Reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Data-Driven Sampling Matrix Boolean Optimization for Energy-Efficient Biomedical Signal Acquisition by Compressive Sensing.
IEEE Trans. Biomed. Circuits Syst., 2017
A Microfluidic Cytometer for Complete Blood Count With a 3.2-Megapixel, 1.1- μm-Pitch Super-Resolution Image Sensor in 65-nm BSI CMOS.
IEEE Trans. Biomed. Circuits Syst., 2017
IEEE J. Solid State Circuits, 2017
ACM J. Emerg. Technol. Comput. Syst., 2017
Demand side management with consumer clusters in cyber-physical smart distribution system considering price-based and reward-based scheduling programs.
IET Cyper-Phys. Syst.: Theory & Appl., 2017
A 7.663-TOPS 8.2-W Energy-efficient FPGA Accelerator for Binary Convolutional Neural Networks.
CoRR, 2017
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017
LTNN: An energy-efficient machine learning accelerator on 3D CMOS-RRAM for layer-wise tensorized neural network.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
Proceedings of the 14th International Conference on Synthesis, 2017
An energy-efficient and high-throughput bitwise CNN on sneak-path-free digital ReRAM crossbar.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
A 7.663-TOPS 8.2-W Energy-efficient FPGA Accelerator for Binary Convolutional Neural Networks (Abstract Only).
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017
A fast online sequential learning accelerator for IoT network intrusion detection: work-in-progress.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017
An efficient 4-way-combined 291 GHz signal source with 1.75 mW peak output power in 65 nm CMOS.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
2016
Synthesis Lectures on Emerging Engineering Technologies, Morgan & Claypool Publishers, ISBN: 978-3-031-02032-2, 2016
DW-AES: A Domain-Wall Nanowire-Based AES for High Throughput and Energy-Efficient Data Encryption in Non-Volatile Memory.
IEEE Trans. Inf. Forensics Secur., 2016
A Zonotoped Macromodeling for Eye-Diagram Verification of High-Speed I/O Links With Jitter and Parameter Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
A Q-Learning Based Self-Adaptive I/O Communication for 2.5D Integrated Many-Core Microprocessor and Memory.
IEEE Trans. Computers, 2016
Machine Learning Based Single-Frame Super-Resolution Processing for Lensless Blood Cell Counting.
Sensors, 2016
A Binary Convolutional Encoder-decoder Network for Real-time Natural Scene Text Processing.
CoRR, 2016
Distributed machine learning based smart-grid energy management with occupant cognition.
Proceedings of the 2016 IEEE International Conference on Smart Grid Communications, 2016
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
An Energy-efficient Adaptive Sub-THz Wireless Interconnect with MIMO-Beamforming between Cores and DRAMs.
Proceedings of the 3rd ACM International Conference on Nanoscale Computing and Communication, 2016
An Energy Efficient CMOS Sub-THz Interconnect with Surface Plasmonic Converter and Oscillator.
Proceedings of the 3rd ACM International Conference on Nanoscale Computing and Communication, 2016
A memristor network with coupled oscillator and crossbar towards L2-norm based machine learning.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
A Compressive-sensing based Testing Vehicle for 3D TSV Pre-bond and Post-bond Testing Data.
Proceedings of the 2016 on International Symposium on Physical Design, 2016
Proceedings of the International SoC Design Conference, 2016
Proceedings of the International Symposium on Integrated Circuits, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Distributed-neuron-network based machine learning on smart-gateway network towards real-time indoor data analytics.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
A convolutional neural network based single-frame super-resolution for lensless blood cell counting.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016
2015
A GPU-Accelerated Parallel Shooting Algorithm for Analysis of Radio Frequency and Microwave Integrated Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2015
3D Many-Core Microprocessor Power Management by Space-Time Multiplexing Based Demand-Supply Matching.
IEEE Trans. Computers, 2015
A Dual-Mode Large-Arrayed CMOS ISFET Sensor for Accurate and High-Throughput pH Sensing in Biomedical Diagnosis.
IEEE Trans. Biomed. Eng., 2015
An Ultra-Low Power CMOS Image Sensor with On-Chip Energy Harvesting and Power Management Capability.
Sensors, 2015
A robust recognition error recovery for micro-flow cytometer by machine-learning enhanced single-frame super-resolution processing.
Integr., 2015
IEEE Des. Test, 2015
A Single-Frame Superresolution Algorithm for Lab-on-a-Chip Lensless Microfluidic Imaging.
IEEE Des. Test, 2015
Proceedings of the Symposium on VLSI Circuits, 2015
Proceedings of the 2015 ACM/IEEE International Workshop on System Level Interconnect Prediction, 2015
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
An energy efficient and low cross-talk CMOS sub-THz I/O with surface-wave modulator and interconnect.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
A 16-channel 24-V 1.8-mA power efficiency enhanced neural/muscular stimulator with exponentially decaying stimulation current.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Indoor positioning by distributed machine-learning based data analytics on smart gateway network.
Proceedings of the 2015 International Conference on Indoor Positioning and Indoor Navigation, 2015
An energy-efficient non-volatile in-memory accelerator for sparse-representation based face recognition.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
A scalable and reconfigurable 2.5D integrated multicore processor on silicon interposer.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Design and Analysis of Wide Frequency-Tuning-Range CMOS 60 GHz VCO by Switching Inductor Loaded Transformer.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Reachability-Based Robustness Verification and Optimization of SRAM Dynamic Stability Under Process Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Variability-Aware Parametric Yield Estimation for Analog/Mixed-Signal Circuits: Concepts, Algorithms, and Challenges.
IEEE Des. Test, 2014
A 64×64 1200fps CMOS ion-image sensor with suppressed fixed-pattern-noise for accurate high-throughput DNA sequencing.
Proceedings of the Symposium on VLSI Circuits, 2014
An energy-efficient 2.5D through-silicon interposer I/O with self-adaptive adjustment of output-voltage swing.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
An overview of new design techniques for high performance CMOS millimeter-wave circuits.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Reinforcement learning based self-adaptive voltage-swing adjustment of 2.5D I/Os for many-core microprocessor and memory communication.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
A zonotoped macromodeling for reachability verification of eye-diagram in high-speed I/O links with jitter.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
A high-sensitivity 135GHz millimeter-wave imager by differential transmission-line loaded split-ring-resonator in 65nm CMOS.
Proceedings of the 44th European Solid State Device Research Conference, 2014
A 131.5GHz, -84dBm sensitivity super-regenerative receiver by zero-phase-shifter coupled oscillator network in 65nm CMOS.
Proceedings of the ESSCIRC 2014, 2014
A thermal resilient integration of many-core microprocessors and main memory by 2.5D TSI I/Os.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Zonotope-based nonlinear model order reduction for fast performance bound analysis of analog circuits with multiple-interval-valued parameter variations.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
A 239-281GHz Sub-THz imager with 100MHz resolution by CMOS direct-conversion receiver with on-chip circular-polarized SIW antenna.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
A 127-140GHz injection-locked signal source with 3.5mW peak output power by zero-phase coupled oscillator network in 65nm CMOS.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
Energy efficient in-memory machine learning for data intensive image-processing by non-volatile domain-wall memory.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
A robustness optimization of SRAM dynamic stability by sensitivity-based reachability analysis.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
Springer, ISBN: 978-1-4939-0550-8, 2014
2013
A 96-GHz Oscillator by High-Q Differential Transmission Line loaded with Complementary Split-Ring Resonator in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
A Dividerless PLL With Low Power and Low Reference Spur by Aperture-Phase Detector and Phase-to-Analog Converter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Reliable 3-D Clock-Tree Synthesis Considering Nonlinear Capacitive TSV Model With Electrical-Thermal-Mechanical Coupling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
An efficient channel clustering and flow rate allocation algorithm for non-uniform microfluidic cooling of 3D integrated circuits.
Integr., 2013
SPECO: Stochastic Perturbation based Clock tree Optimization considering temperature uncertainty.
Integr., 2013
Design and Analysis of CMOS-Based Terahertz Integrated Circuits by Causal Fractional-Order RLGC Transmission Line Model.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2013
Exploiting Parallelism by Data Dependency Elimination: A Case Study of Circuit Simulation Algorithms.
IEEE Des. Test, 2013
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013
SRAM dynamic stability verification by reachability analysis with consideration of threshold voltage variation.
Proceedings of the International Symposium on Physical Design, 2013
An ultralow-power memory-based big-data computing platform by nonvolatile domain-wall nanowire devices.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Cyber-physical management for heterogeneously integrated 3D thousand-core on-chip microprocessor.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A high-frequency transimpedance amplifier for CMOS integrated 2D CMUT array towards 3D ultrasound imaging.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013
3D reconfigurable power switch network for demand-supply matching between multi-output power converters and many-core microprocessors.
Proceedings of the Design, Automation and Test in Europe, 2013
Peak power reduction and workload balancing by space-time multiplexing based demand-supply matching for 3D thousand-core microprocessor.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
A 75.7GHz to 102GHz rotary-traveling-wave VCO by tunable composite right /left hand T-line.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
Stable backward reachability correction for PLL verification with consideration of environmental noise induced jitter.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
Thermal-reliable 3D clock-tree synthesis considering nonlinear electrical-thermal-coupled TSV model.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
Thermal simulator of 3D-IC with modeling of anisotropic TSV conductance and microchannel entrance effects.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
High-speed and low-power 2.5D I/O circuits for memory-logic-integration by through-silicon interposer.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
2012
A Parallel and Incremental Extraction of Variational Capacitance With Stochastic Geometric Moments.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Design Exploration of Hybrid CMOS and Memristor Circuit by New Modified Nodal Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2012
A Fast Non-Monte-Carlo Yield Analysis and Optimization by Stochastic Orthogonal Polynomials.
ACM Trans. Design Autom. Electr. Syst., 2012
Analysis and Modeling of Internal State Variables for Dynamic Effects of Nonvolatile Memory Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Integr., 2012
Design exploration of ultra-low power non-volatile memory based on topological insulator.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
Design of low power 3D hybrid memory by non-volatile CBRAM-crossbar with block-level data-retention.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Decentralized agent based re-clustering for task mapping of tera-scale network-on-chip system.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
High-speed CMOS image sensor for high-throughput lensless microfluidic imaging system.
Proceedings of the Sensors, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
A GPU-accelerated envelope-following method for switching power converter simulation.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 2012 IEEE Biomedical Circuits and Systems Conference, 2012
Fast simulation of hybrid CMOS and STT-MTJ circuits with identified internal state variables.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
Springer, ISBN: 978-1-4614-0787-4, 2012
2011
An EScheduler-Based Data Dependence Analysis and Task Scheduling for Parallel Circuit Simulation.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
Cyber-Physical Thermal Management of 3D Multi-Core Cache-Processor System with Microfluidic Cooling.
J. Low Power Electron., 2011
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011
Proceedings of the 2011 International Symposium on Physical Design, 2011
On the preconditioner of conjugate gradient method - A power grid simulation perspective.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Fast non-monte-carlo transient noise analysis for high-precision analog/RF circuits by stochastic orthogonal polynomials.
Proceedings of the 48th Design Automation Conference, 2011
A 2.1-GHz PLL with -80dBc/-74dBc reference spur based on aperture-phase detector and phase-to-analog converter.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
A structured parallel periodic Arnoldi shooting algorithm for RF-PSS analysis based on GPU platforms.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Design exploration of 3D stacked non-volatile memory by conductive bridge based crossbar.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
3D integration of MEMS and CMOS via Cu-Cu bonding with simultaneous formation of electrical, mechanical and hermetic bonds.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
2010
Fast Analysis of a Large-Scale Inductive Interconnect by Block-Structure-Preserved Macromodeling.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A robust periodic arnoldi shooting algorithm for efficient analysis of large-scale RF/MM ICs.
Proceedings of the 47th Design Automation Conference, 2010
QuickYield: an efficient global-search based parametric yield estimation with performance constraints.
Proceedings of the 47th Design Automation Conference, 2010
A fast analog mismatch analysis by an incremental and stochastic trajectory piecewise linear macromodel.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
Real-time thermal management of 3D multi-core system with fine-grained cooling control.
Proceedings of the IEEE International Conference on 3D System Integration, 2010
2009
ACM Trans. Design Autom. Electr. Syst., 2009
IEEE Des. Test Comput., 2009
PiCAP: a parallel and incremental capacitance extraction considering stochastic process variation.
Proceedings of the 46th Design Automation Conference, 2009
Fast analysis of nontree-clock network considering environmental uncertainty by parameterized and incremental macromodeling.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
Thermal Via Allocation for 3-D ICs Considering Temporally and Spatially Variant Thermal Power.
IEEE Trans. Very Large Scale Integr. Syst., 2008
2007
ACM Trans. Design Autom. Electr. Syst., 2007
General Block Structure-Preserving Reduced Order Modeling of Linear Dynamic Circuits.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 2007 International Symposium on Physical Design, 2007
Proceedings of the 44th Design Automation Conference, 2007
2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
SAMSON: a generalized second-order arnoldi method for reducing multiple source linear network with susceptance.
Proceedings of the 2006 International Symposium on Physical Design, 2006
Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
A fast block structure preserving model order reduction for inverse inductance circuits.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Fast analysis of structured power grid by triangularization based structure preserving model order reduction.
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the 43rd Design Automation Conference, 2006
2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
A sparsified vector potential equivalent circuit model for massively coupled interconnects.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2003
Proceedings of the 40th Design Automation Conference, 2003