Vector potential equivalent circuit based on PEEC inversion. - Hao Yu 001; Lei He 001 (DAC, 2003)

Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction. - Zhenyu Qi 002; Sheldon X.-D. Tan; Hao Yu 001; Lei He 001 (ASP-DAC, 2005)

A wideband hierarchical circuit reduction for massively coupled interconnects. - Hao Yu 001; Lei He 001; Zhenyu Qi 002; Sheldon X.-D. Tan (ASP-DAC, 2005)

A sparsified vector potential equivalent circuit model for massively coupled interconnects. - Hao Yu 001; Lei He 001 (ISCAS (1), 2005)

Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction. - Hao Yu 001; Lei He 001 (ISQED, 2005)

A provably passive and cost-efficient model for inductive interconnects. - Hao Yu 001; Lei He 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Circuit simulation based obstacle-aware Steiner routing. - Yiyu Shi 001; Paul Mesa; Hao Yu 001; Lei He 001 (DAC, 2006)

Fast analysis of structured power grid by triangularization based structure preserving model order reduction. - Hao Yu 001; Yiyu Shi 001; Lei He 001 (DAC, 2006)

Simultaneous power and thermal integrity driven via stapling in 3D ICs. - Hao Yu 001; Joanna Ho; Lei He 001 (ICCAD, 2006)

A fast block structure preserving model order reduction for inverse inductance circuits. - Hao Yu 001; Yiyu Shi 001; Lei He 001; David Smart (ICCAD, 2006)

Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power. - Hao Yu 001; Yiyu Shi 001; Lei He 001; Tanay Karnik (ISLPED, 2006)

SAMSON: a generalized second-order arnoldi method for reducing multiple source linear network with susceptance. - Yiyu Shi 001; Hao Yu 001; Lei He 001 (ISPD, 2006)

Wideband passive multiport model order reduction and realization of RLCM circuits. - Zhenyu Qi 002; Hao Yu 001; Pu Liu; Sheldon X.-D. Tan; Lei He 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Off-chip Decoupling Capacitor Allocation for Chip Package Co-Design. - Hao Yu 001; Chunta Chu; Lei He 001 (DAC, 2007)

Minimal skew clock embedding considering time variant temperature gradient. - Hao Yu 001; Yu Hu 002; Chunchen Liu; Lei He 001 (ISPD, 2007)

General Block Structure-Preserving Reduced Order Modeling of Linear Dynamic Circuits. - Ning Mi; Boyuan Yan; Sheldon X.-D. Tan; Jeffrey Fan; Hao Yu 001 (ISQED, 2007)

Circuit-simulated obstacle-aware Steiner routing. - Yiyu Shi 001; Paul Mesa; Hao Yu 001; Lei He 001 (ACM Trans. Design Autom. Electr. Syst., 2007)

Thermal Via Allocation for 3-D ICs Considering Temporally and Spatially Variant Thermal Power. - Hao Yu 001; Yiyu Shi 001; Lei He 001; Tanay Karnik (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Fast analysis of nontree-clock network considering environmental uncertainty by parameterized and incremental macromodeling. - Hai Wang 002; Hao Yu 001; Sheldon X.-D. Tan (ASP-DAC, 2009)

PiCAP: a parallel and incremental capacitance extraction considering stochastic process variation. - Fang Gong; Hao Yu 001; Lei He 001 (DAC, 2009)

Robust On-Chip Signaling by Staggered and Twisted Bundle. - Hao Yu 001; Lei He 001; Mau-Chung Frank Chang (IEEE Des. Test Comput., 2009)

Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity. - Hao Yu 001; Joanna Ho; Lei He 001 (ACM Trans. Design Autom. Electr. Syst., 2009)

Real-time thermal management of 3D multi-core system with fine-grained cooling control. - Hanhua Qian; Xiwei Huang; Hao Yu 001; Chip-Hong Chang (3DIC, 2010)

A fast analog mismatch analysis by an incremental and stochastic trajectory piecewise linear macromodel. - Hao Yu 001; Xuexin Liu; Hai Wang 002; Sheldon X.-D. Tan (ASP-DAC, 2010)

QuickYield: an efficient global-search based parametric yield estimation with performance constraints. - Fang Gong; Hao Yu 001; Yiyu Shi 001; Daesoo Kim; Junyan Ren; Lei He 001 (DAC, 2010)

A robust periodic arnoldi shooting algorithm for efficient analysis of large-scale RF/MM ICs. - Xuexin Liu; Hao Yu 001; Sheldon X.-D. Tan (DAC, 2010)

A new modified nodal analysis for nano-scale memristor circuit simulation. - Hao Yu 001; Wei Fei (ISCAS, 2010)

Fast Analysis of a Large-Scale Inductive Interconnect by Block-Structure-Preserved Macromodeling. - Hao Yu 001; Chunta Chu; Yiyu Shi 001; David Smart; Lei He 001; Sheldon X.-D. Tan (IEEE Trans. Very Large Scale Integr. Syst., 2010)

3D integration of MEMS and CMOS via Cu-Cu bonding with simultaneous formation of electrical, mechanical and hermetic bonds. - Revanth Nadipalli; Ji Fan; Holden King Ho Li; Keng Hoong Wee; Hao Yu 001; Chuan Seng Tan (3DIC, 2011)

Design exploration of 3D stacked non-volatile memory by conductive bridge based crossbar. - Yuhao Wang 002; Chun Zhang; Revanth Nadipalli; Hao Yu 001; Roshan Weerasekera (3DIC, 2011)

A structured parallel periodic Arnoldi shooting algorithm for RF-PSS analysis based on GPU platforms. - Xuexin Liu; Hao Yu 001; Jacob Relles; Sheldon X.-D. Tan (ASP-DAC, 2011)

A 2.1-GHz PLL with -80dBc/-74dBc reference spur based on aperture-phase detector and phase-to-analog converter. - Deyun Cai; Haipeng Fu; Junyan Ren; Wei Li 038; Ning Li 007; Hao Yu 001; Kiat Seng Yeo (A-SSCC, 2011)

Fast non-monte-carlo transient noise analysis for high-precision analog/RF circuits by stochastic orthogonal polynomials. - Fang Gong; Hao Yu 001; Lei He 001 (DAC, 2011)

On the preconditioner of conjugate gradient method - A power grid simulation perspective. - Chung-Han Chou; Nien-Yu Tsai; Hao Yu 001; Che-Rung Lee; Yiyu Shi 001; Shih-Chieh Chang (ICCAD, 2011)

Stochastic analog circuit behavior modeling by point estimation method. - Fang Gong; Hao Yu 001; Lei He 001 (ISPD, 2011)

NEMS based thermal management for 3D many-core system. - Xiwei Huang; Hao Yu 001; Wei Zhang 012 (NANOARCH, 2011)

Cyber-Physical Thermal Management of 3D Multi-Core Cache-Processor System with Microfluidic Cooling. - Hanhua Qian; Xiwei Huang; Hao Yu 001; Chip-Hong Chang (J. Low Power Electron., 2011)

An EScheduler-Based Data Dependence Analysis and Task Scheduling for Parallel Circuit Simulation. - Xiaoming Chen 003; Wei Wu; Yu Wang 002; Hao Yu 001; Huazhong Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs. - Ruijing Shen; Sheldon X.-D. Tan; Hao Yu 001 (Springer, 2012)

A 96×96 1V ultra-low power CMOS image sensor for biomedical application. - Tongxi Wang; Xiwei Huang; Mei Yan; Hao Yu 001; Kiat Seng Yeo; Ismail Cevik; Suat U. Ay (APCCAS, 2012)

Fast simulation of hybrid CMOS and STT-MTJ circuits with identified internal state variables. - Yang Shang; Wei Fei; Hao Yu 001 (ASP-DAC, 2012)

A super-resolution CMOS image sensor for bio-microfluidic imaging. - Tongxi Wang; Xiwei Huang; Qixiang Jia; Mei Yan; Hao Yu 001; Kiat Seng Yeo (BioCAS, 2012)

A GPU-accelerated envelope-following method for switching power converter simulation. - Xuexin Liu; Sheldon X.-D. Tan; Hai Wang 002; Hao Yu 001 (DATE, 2012)

Fair energy resource allocation by minority game algorithm for smart buildings. - Chun Zhang; Wei Wu; Hantao Huang; Hao Yu 001 (DATE, 2012)

High-speed CMOS image sensor for high-throughput lensless microfluidic imaging system. - Mei Yan; Xiwei Huang; Qixiang Jia; Revanth Nadipalli; Tongxi Wang; Yang Shang; Hao Yu 001; Minkyu Je; Kiat Seng Yeo (Sensors, Cameras, and Systems for Industrial and Scientific Applications, 2012)

Distributed thermal-aware task scheduling for 3D Network-on-Chip. - Yingnan Cui; Wei Zhang 012; Hao Yu 001 (ICCD, 2012)

Decentralized agent based re-clustering for task mapping of tera-scale network-on-chip system. - Yingnan Cui; Wei Zhang 012; Hao Yu 001 (ISCAS, 2012)

Design of low power 3D hybrid memory by non-volatile CBRAM-crossbar with block-level data-retention. - Yuhao Wang 002; Chun Zhang; Hao Yu 001; Wei Zhang 012 (ISLPED, 2012)

Design exploration of ultra-low power non-volatile memory based on topological insulator. - Yuhao Wang 002; Hao Yu 001 (NANOARCH, 2012)

Fast timing analysis of clock networks considering environmental uncertainty. - Hai Wang 002; Hao Yu 001; Sheldon X.-D. Tan (Integr., 2012)

Analysis and Modeling of Internal State Variables for Dynamic Effects of Nonvolatile Memory Devices. - Yang Shang; Wei Fei; Hao Yu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A Fast Non-Monte-Carlo Yield Analysis and Optimization by Stochastic Orthogonal Polynomials. - Fang Gong; Xuexin Liu; Hao Yu 001; Sheldon X.-D. Tan; Junyan Ren; Lei He 001 (ACM Trans. Design Autom. Electr. Syst., 2012)

Design Exploration of Hybrid CMOS and Memristor Circuit by New Modified Nodal Analysis. - Wei Fei; Hao Yu 001; Wei Zhang 012; Kiat Seng Yeo (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A Parallel and Incremental Extraction of Variational Capacitance With Stochastic Geometric Moments. - Fang Gong; Hao Yu 001; Lingli Wang; Lei He 001 (IEEE Trans. Very Large Scale Integr. Syst., 2012)

High-speed and low-power 2.5D I/O circuits for memory-logic-integration by through-silicon interposer. - Jiacheng Wang 001; Shunli Ma; Sai Manoj Pudukotai Dinakarrao; Mingbin Yu; Roshan Weerasekera; Hao Yu 001 (3DIC, 2013)

Thermal simulator of 3D-IC with modeling of anisotropic TSV conductance and microchannel entrance effects. - Hanhua Qian; Hao Liang 003; Chip-Hong Chang; Wei Zhang 012; Hao Yu 001 (ASP-DAC, 2013)

Thermal-reliable 3D clock-tree synthesis considering nonlinear electrical-thermal-coupled TSV model. - Yang Shang; Chun Zhang; Hao Yu 001; Chuan Seng Tan; Xin Zhao 001; Sung Kyu Lim (ASP-DAC, 2013)

Stable backward reachability correction for PLL verification with consideration of environmental noise induced jitter. - Yang Song; Haipeng Fu; Hao Yu 001; Guoyong Shi (ASP-DAC, 2013)

A 75.7GHz to 102GHz rotary-traveling-wave VCO by tunable composite right /left hand T-line. - Shunli Ma; Wei Fei; Hao Yu 001; Junyan Ren (CICC, 2013)

Peak power reduction and workload balancing by space-time multiplexing based demand-supply matching for 3D thousand-core microprocessor. - Sai Manoj Pudukotai Dinakarrao; Kanwen Wang; Hao Yu 001 (DAC, 2013)

3D reconfigurable power switch network for demand-supply matching between multi-output power converters and many-core microprocessors. - Kanwen Wang; Hao Yu 001; Benfei Wang; Chun Zhang (DATE, 2013)

A high-frequency transimpedance amplifier for CMOS integrated 2D CMUT array towards 3D ultrasound imaging. - Xiwei Huang; Jia Hao Cheong; Hyouk-Kyu Cha; Hongbin Yu; Minkyu Je; Hao Yu 001 (EMBC, 2013)

Cyber-physical management for heterogeneously integrated 3D thousand-core on-chip microprocessor. - Sai Manoj Pudukotai Dinakarrao; Hao Yu 001 (ISCAS, 2013)

A 5-bit 1.25GS/s 4.7mW delay-based pipelined ADC in 65nm CMOS. - Ali Mesgarani; Haipeng Fu; Mei Yan; A. Tekin; Hao Yu 001; Suat U. Ay (ISCAS, 2013)

An ultralow-power memory-based big-data computing platform by nonvolatile domain-wall nanowire devices. - Yuhao Wang 002; Hao Yu 001 (ISLPED, 2013)

SRAM dynamic stability verification by reachability analysis with consideration of threshold voltage variation. - Yang Song; Hao Yu 001; Sai Manoj Pudukotai Dinakarrao; Guoyong Shi (ISPD, 2013)

On the futility of thermal through-silicon-vias. - Chung-Han Chou; Nien-Yu Tsai; Hao Yu 001; Yiyu Shi 001; Jui-Hung Chien; Shih-Chieh Chang (VLSI-DAT, 2013)

Exploiting Parallelism by Data Dependency Elimination: A Case Study of Circuit Simulation Algorithms. - Wei Wu; Fang Gong; Rahul Krishnan; Lei He 001; Hao Yu 001 (IEEE Des. Test, 2013)

Design and Analysis of CMOS-Based Terahertz Integrated Circuits by Causal Fractional-Order RLGC Transmission Line Model. - Yang Shang; Hao Yu 001; Wei Fei (IEEE J. Emerg. Sel. Topics Circuits Syst., 2013)

SPECO: Stochastic Perturbation based Clock tree Optimization considering temperature uncertainty. - Sina Basir-Kazeruni; Hao Yu 001; Fang Gong; Yu Hu 002; Chunchen Liu; Lei He 001 (Integr., 2013)

An efficient channel clustering and flow rate allocation algorithm for non-uniform microfluidic cooling of 3D integrated circuits. - Hanhua Qian; Chip-Hong Chang; Hao Yu 001 (Integr., 2013)

Reliable 3-D Clock-Tree Synthesis Considering Nonlinear Capacitive TSV Model With Electrical-Thermal-Mechanical Coupling. - Sai Manoj Pudukotai Dinakarrao; Hao Yu 001; Yang Shang; Chuan Seng Tan; Sung Kyu Lim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Stochastic Behavioral Modeling and Analysis for Analog/Mixed-Signal Circuits. - Fang Gong; Sina Basir-Kazeruni; Lei He 001; Hao Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

A Dividerless PLL With Low Power and Low Reference Spur by Aperture-Phase Detector and Phase-to-Analog Converter. - Deyun Cai; Haipeng Fu; Junyan Ren; Wei Li 038; Ning Li 007; Hao Yu 001; Kiat Seng Yeo (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A 96-GHz Oscillator by High-Q Differential Transmission Line loaded with Complementary Split-Ring Resonator in 65-nm CMOS. - Wei Fei; Hao Yu 001; Yang Shang; Deyun Cai; Junyan Ren (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Design Exploration of Emerging Nano-scale Non-volatile Memory. - Hao Yu 001; Yuhao Wang 002 (Springer, 2014)

A robustness optimization of SRAM dynamic stability by sensitivity-based reachability analysis. - Yang Song; Sai Manoj Pudukotai Dinakarrao; Hao Yu 001 (ASP-DAC, 2014)

Energy efficient in-memory machine learning for data intensive image-processing by non-volatile domain-wall memory. - Hao Yu 001; Yuhao Wang 002; Shuai Chen; Wei Fei; Chuliang Weng; Junfeng Zhao 003; Zhulin Wei (ASP-DAC, 2014)

A 127-140GHz injection-locked signal source with 3.5mW peak output power by zero-phase coupled oscillator network in 65nm CMOS. - Yang Shang; Hao Yu 001; Peng Li; Xiaojun Bi 003; Minkyu Je (CICC, 2014)

A 239-281GHz Sub-THz imager with 100MHz resolution by CMOS direct-conversion receiver with on-chip circular-polarized SIW antenna. - Yang Shang; Hao Yu 001; Chang Yang; Yuan Liang 004; Wei Meng Lim (CICC, 2014)

Zonotope-based nonlinear model order reduction for fast performance bound analysis of analog circuits with multiple-interval-valued parameter variations. - Yang Song; Sai Manoj Pudukotai Dinakarrao; Hao Yu 001 (DATE, 2014)

Energy efficient in-memory AES encryption based on nonvolatile domain-wall nanowire. - Yuhao Wang 002; Hao Yu 001; Dennis Sylvester; Pingfan Kong (DATE, 2014)

A thermal resilient integration of many-core microprocessors and main memory by 2.5D TSI I/Os. - Sih-Sian Wu; Kanwen Wang; Sai Manoj Pudukotai Dinakarrao; Tsung-Yi Ho; Mingbin Yu; Hao Yu 001 (DATE, 2014)

A 131.5GHz, -84dBm sensitivity super-regenerative receiver by zero-phase-shifter coupled oscillator network in 65nm CMOS. - Shunli Ma; Hao Yu 001; Yang Shang; Wei Meng Lim; Junyan Ren (ESSCIRC, 2014)

A high-sensitivity 135GHz millimeter-wave imager by differential transmission-line loaded split-ring-resonator in 65nm CMOS. - Yang Shang; Hao Yu 001; Chang Yang; Sanming Hu; Minkyu Je (ESSDERC, 2014)

A zonotoped macromodeling for reachability verification of eye-diagram in high-speed I/O links with jitter. - Sai Manoj Pudukotai Dinakarrao; Hao Yu 001; Chenjie Gu; Cheng Zhuo (ICCAD, 2014)

Reinforcement learning based self-adaptive voltage-swing adjustment of 2.5D I/Os for many-core microprocessor and memory communication. - Hantao Huang; Sai Manoj Pudukotai Dinakarrao; Dongjun Xu; Hao Yu 001; Zhigang Hao (ICCAD, 2014)

An overview of new design techniques for high performance CMOS millimeter-wave circuits. - Shunli Ma; Junyan Ren; Hao Yu 001 (ISIC, 2014)

An energy-efficient 2.5D through-silicon interposer I/O with self-adaptive adjustment of output-voltage swing. - Dongjun Xu; Sai Manoj Pudukotai Dinakarrao; Hantao Huang; Ningmei Yu; Hao Yu 001 (ISLPED, 2014)

A 64×64 1200fps CMOS ion-image sensor with suppressed fixed-pattern-noise for accurate high-throughput DNA sequencing. - Xiwei Huang; Fei Wang; Jing Guo; Mei Yan; Hao Yu 001; Kiat Seng Yeo (VLSIC, 2014)

Variability-Aware Parametric Yield Estimation for Analog/Mixed-Signal Circuits: Concepts, Algorithms, and Challenges. - Fang Gong; Hao Yu 001; Yiyu Shi 001; Lei He 001 (IEEE Des. Test, 2014)

Reachability-Based Robustness Verification and Optimization of SRAM Dynamic Stability Under Process Variations. - Yang Song; Hao Yu 001; Sai Manoj Pudukotai Dinakarrao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Design and Analysis of Wide Frequency-Tuning-Range CMOS 60 GHz VCO by Switching Inductor Loaded Transformer. - Wei Fei; Hao Yu 001; Haipeng Fu; Junyan Ren; Kiat Seng Yeo (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Nonvolatile CBRAM-Crossbar-Based 3-D-Integrated Hybrid Memory for Data Retention. - Yuhao Wang 002; Hao Yu 001; Wei Zhang 012 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A CMOS THz-sensing system towards label-free DNA sequencing. - Xiwei Huang; Yu Jiang 004; Yang Shang; Hao Yu 001; Lingling Sun (ASICON, 2015)

A 64×64 1200fps dual-mode CMOS ion-image sensor for accurate DNA sequencing. - Xiwei Huang; Jing Guo; Mei Yan; Hao Yu 001 (ASP-DAC, 2015)

A 201 mV/pH, 375 fps and 512×576 CMOS ISFET sensor in 65nm CMOS technology. - Yu Jiang 004; Xu Liu 002; Xiwei Huang; Jing Guo; Mei Yan; Hao Yu 001; Jui-Cheng Huang; Kenny Cheng-Hsiang Hsieh; Tung-Tsun Chen (CICC, 2015)

A scalable and reconfigurable 2.5D integrated multicore processor on silicon interposer. - Jie Lin; Shikai Zhu; Zhiyi Yu; Dongjun Xu; Sai Manoj P. D.; Hao Yu 001 (CICC, 2015)

An energy-efficient non-volatile in-memory accelerator for sparse-representation based face recognition. - Yuhao Wang 002; Hantao Huang; Leibin Ni; Hao Yu 001; Mei Yan; Chuliang Weng; Wei Yang; Junfeng Zhao 003 (DATE, 2015)

Indoor positioning by distributed machine-learning based data analytics on smart gateway network. - Yuehua Cai; Suleman Khalid Rai; Hao Yu 001 (IPIN, 2015)

A 16-channel 24-V 1.8-mA power efficiency enhanced neural/muscular stimulator with exponentially decaying stimulation current. - Xu Liu 002; Lei Yao; Peng Li; Mei Yan; Shih-Cheng Yen; Hao Yu 001; Minkyu Je; Yong Ping Xu (ISCAS, 2015)

A body-biasing of readout circuit for STT-RAM with improved thermal reliability. - Lun Yang; Yuanqing Cheng; Yuhao Wang 002; Hao Yu 001; Weisheng Zhao; Aida Todri-Sanial (ISCAS, 2015)

An energy efficient and low cross-talk CMOS sub-THz I/O with surface-wave modulator and interconnect. - Yuan Liang 004; Hao Yu 001; Junfeng Zhao 003; Wei Yang; Yuangang Wang (ISLPED, 2015)

Optimizing Boolean embedding matrix for compressive sensing in RRAM crossbar. - Yuhao Wang 002; Xin Li 001; Hao Yu 001; Leibin Ni; Wei Yang; Chuliang Weng; Junfeng Zhao 003 (ISLPED, 2015)

Smart I/Os: a data-pattern aware 2.5D interconnect with space-time multiplexing. - Sai Manoj P. D.; Kanwen Wang; Hantao Huang; Hao Yu 001 (SLIP, 2015)

A 23mW face recognition accelerator in 40nm CMOS with mostly-read 5T memory. - Dongsuk Jeon; Qing Dong 001; Yejoong Kim; Xiaolong Wang; Shuai Chen; Hao Yu 001; David T. Blaauw; Dennis Sylvester (VLSIC, 2015)

A Single-Frame Superresolution Algorithm for Lab-on-a-Chip Lensless Microfluidic Imaging. - Xiwei Huang; Hao Yu 001; Xu Liu 002; Yu Jiang 004; Mei Yan (IEEE Des. Test, 2015)

A 2.5-D Memory-Logic Integration With Data-Pattern-Aware Memory Controller. - Dongjun Xu; Sai Manoj P. D.; Kanwen Wang; Hao Yu 001; Ningmei Yu; Mingbin Yu (IEEE Des. Test, 2015)

A robust recognition error recovery for micro-flow cytometer by machine-learning enhanced single-frame super-resolution processing. - Xiwei Huang; Xiaolong Wang; Mei Yan; Hao Yu 001 (Integr., 2015)

An Ultra-Low Power CMOS Image Sensor with On-Chip Energy Harvesting and Power Management Capability. - Ismail Cevik; Xiwei Huang; Hao Yu 001; Mei Yan; Suat U. Ay (Sensors, 2015)

A Dual-Mode Large-Arrayed CMOS ISFET Sensor for Accurate and High-Throughput pH Sensing in Biomedical Diagnosis. - Xiwei Huang; Hao Yu 001; Xu Liu 002; Yu Jiang 004; Mei Yan; Dongping Wu (IEEE Trans. Biomed. Eng., 2015)

3D Many-Core Microprocessor Power Management by Space-Time Multiplexing Based Demand-Supply Matching. - Sai Manoj P. D.; Hao Yu 001; Kanwen Wang (IEEE Trans. Computers, 2015)

A GPU-Accelerated Parallel Shooting Algorithm for Analysis of Radio Frequency and Microwave Integrated Circuits. - Xuexin Liu; Hao Yu 001; Sheldon X.-D. Tan (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A 3D multi-layer CMOS-RRAM accelerator for neural network. - Hantao Huang; Leibin Ni; Yuhao Wang 002; Hao Yu 001; Zongwei Wang 001; Yimao Cai; Ru Huang 001 (3DIC, 2016)

An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar. - Leibin Ni; Yuhao Wang 002; Hao Yu 001; Wei Yang; Chuliang Weng; Junfeng Zhao 003 (ASP-DAC, 2016)

A convolutional neural network based single-frame super-resolution for lensless blood cell counting. - Xiwei Huang; Yu Jiang 004; Hang Xu 001; Xu Liu 002; Han Wei Hou; Mei Yan; Hao Yu 001 (BioCAS, 2016)

Distributed-neuron-network based machine learning on smart-gateway network towards real-time indoor data analytics. - Hantao Huang; Yuehua Cai; Hao Yu 001 (DATE, 2016)

Lab-on-CMOS: A multi-modal CMOS sensor platform towards personalized DNA sequencing. - Yu Jiang 004; Xu Liu 002; Xiwei Huang; Yang Shang; Mei Yan; Hao Yu 001 (ISCAS, 2016)

On-line machine learning accelerator on digital RRAM-crossbar. - Leibin Ni; Hantao Huang; Hao Yu 001 (ISCAS, 2016)

Fully integrated pseudo differential K-band power amplifier in 0.13um standard CMOS. - Pengwei Chen; Jin He 002; Jiang Luo; Hao Wang 046; Sheng Chang; Qijun Huang; Hao Yu 001; Xiaopeng Yu (ISIC, 2016)

Low-power and real-time computer vision on-chip. - Wei Pang; Hantao Huang; Fengwei An; Hao Yu 001 (ISOCC, 2016)

A Compressive-sensing based Testing Vehicle for 3D TSV Pre-bond and Post-bond Testing Data. - Hantao Huang; Hao Yu 001; Cheng Zhuo; Fengbo Ren (ISPD, 2016)

Energy Optimization of Racetrack Memory-Based SIMON Block Cipher. - Suman Deb; Anupam Chattopadhyay; Hao Yu 001 (ISVLSI, 2016)

A memristor network with coupled oscillator and crossbar towards L2-norm based machine learning. - Leibin Ni; Hantao Huang; Hao Yu 001 (NANOARCH, 2016)

An Energy Efficient CMOS Sub-THz Interconnect with Surface Plasmonic Converter and Oscillator. - Yuan Liang 004; Guangyin Feng; Xiaojian Fu; Hao Yu 001 (NANOCOM, 2016)

An Energy-efficient Adaptive Sub-THz Wireless Interconnect with MIMO-Beamforming between Cores and DRAMs. - Zichuan Liu; Yuan Liang 004; Nan Li; Guangyin Feng; Hao Yu 001; Shaojie Chen (NANOCOM, 2016)

Racetrack memory-based encoder/decoder for low-power interconnect architectures. - Suman Deb; Leibin Ni; Hao Yu 001; Anupam Chattopadhyay (SAMOS, 2016)

Distributed machine learning based smart-grid energy management with occupant cognition. - Hang Xu 001; Hantao Huang; Suleman Khalid Rai; Hao Yu 001 (SmartGridComm, 2016)

A Binary Convolutional Encoder-decoder Network for Real-time Natural Scene Text Processing. - Zichuan Liu; Yixing Li; Fengbo Ren; Hao Yu 001 (CoRR, 2016)

Editorial. - Chip-Hong Chang; Tae-Hyoung Kim; Hao Yu 001 (J. Circuits Syst. Comput., 2016)

Machine Learning Based Single-Frame Super-Resolution Processing for Lensless Blood Cell Counting. - Xiwei Huang; Yu Jiang 004; Xu Liu 002; Hang Xu 001; Zhi Han; Hailong Rong; Haiping Yang; Mei Yan; Hao Yu 001 (Sensors, 2016)

A Q-Learning Based Self-Adaptive I/O Communication for 2.5D Integrated Many-Core Microprocessor and Memory. - Sai Manoj P. D.; Hao Yu 001; Hantao Huang; Dongjun Xu (IEEE Trans. Computers, 2016)

A Zonotoped Macromodeling for Eye-Diagram Verification of High-Speed I/O Links With Jitter and Parameter Variations. - Leibin Ni; Sai Manoj P. D.; Yang Song; Chenjie Gu; Hao Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

DW-AES: A Domain-Wall Nanowire-Based AES for High Throughput and Energy-Efficient Data Encryption in Non-Volatile Memory. - Yuhao Wang 002; Leibin Ni; Chip-Hong Chang; Hao Yu 001 (IEEE Trans. Inf. Forensics Secur., 2016)

Non-Volatile In-Memory Computing by Spintronics - Hao Yu 001; Leibin Ni; Yuhao Wang 002 (Morgan & Claypool Publishers, 2016)

Fast food safety screening with CMOS high-sensitivity large-arrayed ISFET sensor. - Yu Jiang 004; Philippe Coquet; Hao Yu 001 (BioCAS, 2017)

An efficient 4-way-combined 291 GHz signal source with 1.75 mW peak output power in 65 nm CMOS. - Alit Apriyana; Guangyin Feng; Yang Shang; Jincai Wen; Lingling Sun; Hao Yu 001 (CICC, 2017)

A fast online sequential learning accelerator for IoT network intrusion detection: work-in-progress. - Hantao Huang; Suleman Khalid Rai; Wenye Liu; Hao Yu 001 (CODES+ISSS, 2017)

NucleiNet: A convolutional encoder-decoder network for bio-image denoising. - Zichuan Liu; Yifei Hu; Hang Xu 001; Lamees Nasser; Philippe Coquet; Thomas Boudier; Hao Yu 001 (EMBC, 2017)

A 7.663-TOPS 8.2-W Energy-efficient FPGA Accelerator for Binary Convolutional Neural Networks (Abstract Only). - Yixing Li; Zichuan Liu; Kai Xu 007; Hao Yu 001; Fengbo Ren (FPGA, 2017)

An energy-efficient and high-throughput bitwise CNN on sneak-path-free digital ReRAM crossbar. - Leibin Ni; Zichuan Liu; Wenhao Song; J. Joshua Yang; Hao Yu 001; Kanwen Wang; Yuangang Wang (ISLPED, 2017)

Developing a web-based symbolic circuit analysis tool for learning and design aid. - Hao Yu 001; Guoyong Shi (SMACD, 2017)

LTNN: An energy-efficient machine learning accelerator on 3D CMOS-RRAM for layer-wise tensorized neural network. - Hantao Huang; Leibin Ni; Hao Yu 001 (SoCC, 2017)

Energy efficient VLSI circuits for machine learning on-chip. - Hao Yu 001 (VLSI-DAT, 2017)

A 7.663-TOPS 8.2-W Energy-efficient FPGA Accelerator for Binary Convolutional Neural Networks. - Yixing Li; Zichuan Liu; Kai Xu 007; Hao Yu 001; Fengbo Ren (CoRR, 2017)

Demand side management with consumer clusters in cyber-physical smart distribution system considering price-based and reward-based scheduling programs. - Srikanth Reddy K; Lokesh Kumar Panwar; Bijaya K. Panigrahi; Rajesh Kumar 002; Hao Yu 001 (IET Cyper-Phys. Syst.: Theory & Appl., 2017)

Distributed In-Memory Computing on Binary RRAM Crossbar. - Leibin Ni; Hantao Huang; Zichuan Liu; Rajiv V. Joshi; Hao Yu 001 (ACM J. Emerg. Technol. Comput. Syst., 2017)

A 23-mW Face Recognition Processor with Mostly-Read 5T Memory in 40-nm CMOS. - Dongsuk Jeon; Qing Dong 001; Yejoong Kim; Xiaolong Wang; Shuai Chen; Hao Yu 001; David T. Blaauw; Dennis Sylvester (IEEE J. Solid State Circuits, 2017)

A Microfluidic Cytometer for Complete Blood Count With a 3.2-Megapixel, 1.1- μm-Pitch Super-Resolution Image Sensor in 65-nm BSI CMOS. - Xu Liu 002; Xiwei Huang; Yu Jiang 004; Hang Xu 001; Jing Guo; Han Wei Hou; Mei Yan; Hao Yu 001 (IEEE Trans. Biomed. Circuits Syst., 2017)

Data-Driven Sampling Matrix Boolean Optimization for Energy-Efficient Biomedical Signal Acquisition by Compressive Sensing. - Yuhao Wang 002; Xin Li 001; Kai Xu 007; Fengbo Ren; Hao Yu 001 (IEEE Trans. Biomed. Circuits Syst., 2017)

A Multiagent Minority-Game-Based Demand-Response Management of Smart Buildings Toward Peak Load Reduction. - Hantao Huang; Yuehua Cai; Hang Xu 001; Hao Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator. - Sai Manoj P. D.; Jie Lin; Shikai Zhu; Yingying Yin; Xu Liu 002; Xiwei Huang; Chongshen Song; Wenqi Zhang; Mei Yan; Zhiyi Yu; Hao Yu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

SqueezedText: A Real-Time Scene Text Recognition by Binary Convolutional Encoder-Decoder Network. - Zichuan Liu; Yixing Li; Fengbo Ren; Wang Ling Goh; Hao Yu 001 (AAAI, 2018)

Symbolic Circuit Reduction for Multistage Amplifier Macromodeling. - Hao Yu 001; Guoyong Shi (APCCAS, 2018)

A Nano-Filter-Integrated CMOS Image Sensor for Fluorescent Biomedical Imaging. - Yu Jiang 004; Hao Yu 001; Xiaojian Fu; Chathuranga Hettiarachchi; He Xu; Ye Li; Tien-Hoa Nguyen; Longtao Dong; Cuong Dang; Qing Zhang (BioCAS, 2018)

D-Band Surface-Wave Modulator and Signal Source with 40 dB Extinction Ratio and 3.7mW Output Power in 65 nm CMOS. - Yuan Liang 004; Hao Yu 001; Chirn Chye Boon; Chenyang Li 008; Dietmar Kissinger; Yong Wang (ESSCIRC, 2018)

A D-Band Amplifier in 65 nm Bulk CMOS for Short-Distance Data Center Communication. - Jiang Luo; Jin He 002; Guangyin Feng; Alit Apriyana; Ya Fang; Zhe Xue; Qijun Huang; Hao Yu 001 (IEEE Access, 2018)

DEEPEYE: A Compact and Accurate Video Comprehension at Terminal Devices Compressed with Quantization and Tensorization. - Yuan Cheng; Guangya Li; Hai-Bao Chen; Sheldon X.-D. Tan; Hao Yu 001 (CoRR, 2018)

Q-Learning-Based Voltage-Swing Tuning and Compensation for 2.5-D Memory-Logic Integration. - Dongjun Xu; Ningmei Yu; Hantao Huang; Sai Manoj Pudukotai Dinakarrao; Hao Yu 001 (IEEE Des. Test, 2018)

A GPU-Outperforming FPGA Accelerator Architecture for Binary Convolutional Neural Networks. - Yixing Li; Zichuan Liu; Kai Xu 007; Hao Yu 001; Fengbo Ren (ACM J. Emerg. Technol. Comput. Syst., 2018)

A High-Sensitivity Potentiometric 65-nm CMOS ISFET Sensor for Rapid E. coli Screening. - Yu Jiang 004; Xu Liu 002; Tran Chien Dang; Xiwei Huang; Hao Feng; Qing Zhang; Hao Yu 001 (IEEE Trans. Biomed. Circuits Syst., 2018)

Distributed Machine Learning on Smart-Gateway Network toward Real-Time Smart-Grid Energy Management with Behavior Cognition. - Hantao Huang; Hang Xu 001; Yuehua Cai; Suleman Khalid Rai; Hao Yu 001 (ACM Trans. Design Autom. Electr. Syst., 2018)

A Low-Power High-Throughput In-Memory CMOS-ReRAM Accelerator for Large-Scale Deep Residual Neural Networks. - Yuan Cheng; Ngai Wong 001; Xiong Liu; Leibin Ni; Hai-Bao Chen; Hao Yu 001 (ASICON, 2019)

ANT-UNet: Accurate and Noise-Tolerant Segmentation for Pathology Image Processing. - Yufei Chen 007; Qinming Zhang; Tingtao Li; Hao Yu 001; Mei Tian; Cheng Zhuo (BioCAS, 2019)

Fast video facial expression recognition by deeply tensor-compressed LSTM neural network on mobile device. - Peining Zhen; Bin Liu; Yuan Cheng; Hai-Bao Chen; Hao Yu 001 (SEC, 2019)

DEEPEYE: A Deeply Tensor-Compressed Neural Network Hardware Accelerator: Invited Paper. - Yuan Cheng; Guangya Li; Ngai Wong 001; Hai-Bao Chen; Hao Yu 001 (ICCAD, 2019)

A 307-fps 351.7-GOPs/W Deep Learning FPGA Accelerator for Real-Time Scene Text Recognition. - Shirui Zhao; Fengwei An; Hao Yu 001 (FPT, 2019)

A large-scale in-memory computing for deep neural network with trained quantization. - Yuan Cheng; Chao Wang; Hai-Bao Chen; Hao Yu 001 (Integr., 2019)

3D FEM Analysis of High-Frequency AlN-Based PMUT Arrays on Cavity SOI. - Wenjuan Liu; Leming He; Xubo Wang; Jia Zhou; Weijiang Xu; Nikolay Smagin; Malika Toubal; Hao Yu 001; Yuandong Gu; Jinghui Xu; Denis Remiens; Junyan Ren (Sensors, 2019)

A 5-10-Gb/s 12.5-mW Source Synchronous I/O Interface With 3-D Flip Chip Package. - Shunli Ma; Hao Yu 001; Qun Jane Gu; Junyan Ren (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Spoof Plasmon Interconnects - Communications Beyond RC Limit. - Soumitra Roy Joy; Mikhail Erementchouk; Hao Yu 001; Pinaki Mazumder (IEEE Trans. Commun., 2019)

Guest Editorial: Special Issue on New Trends in Smart Chips and Smart Hardware. - Guang-Bin Huang; E. S. Eleftheriou; Dhireesha Kudithipudi; Jonathan Tapson; Hao Yu 001 (IEEE Trans. Emerg. Top. Comput. Intell., 2019)

A 34-FPS 698-GOP/s/W Binarized Deep Neural Network-Based Natural Scene Text Interpretation Accelerator for Mobile Edge Computing. - Yixing Li; Zichuan Liu; Wenye Liu; Yu Jiang 004; Yongliang Wang; Wang Ling Goh; Hao Yu 001; Fengbo Ren (IEEE Trans. Ind. Electron., 2019)

LTNN: A Layerwise Tensorized Compression of Multilayer Neural Network. - Hantao Huang; Hao Yu 001 (IEEE Trans. Neural Networks Learn. Syst., 2019)

Design and Analysis of $D$ -Band On-Chip Modulator and Signal Source Based on Split-Ring Resonator. - Yuan Liang 004; Chirn Chye Boon; Chenyang Li 008; Xiao-Lan Tang; Herman Jalli Ng; Dietmar Kissinger; Yong Wang; Qingfeng Zhang; Hao Yu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2019)

An Anomaly Comprehension Neural Network for Surveillance Videos on Terminal Devices. - Yuan Cheng; Guangtai Huang; Peining Zhen; Bin Liu; Hai-Bao Chen; Ngai Wong 001; Hao Yu 001 (DATE, 2020)

Energy-Efficient Machine Learning Accelerator for Binary Neural Networks. - Wei Mao 002; Zhihua Xiao; Peng Xu; Hongwei Ren; Dingbang Liu; Shirui Zhao; Fengwei An; Hao Yu 001 (ACM Great Lakes Symposium on VLSI, 2020)

Analog Integrated Circuits Based on Wafer-Level Two-Dimensional MoS2 Materials With Physical and SPICE Model. - Shunli Ma; Yan Wang 097; Xinyu Chen; Tianxiang Wu; Xi Wang; Hongwei Tang; Yuting Yao; Hao Yu 001; Yaochen Sheng; Jingyi Ma; Junyan Ren; Wenzhong Bao (IEEE Access, 2020)

HOTCAKE: Higher Order Tucker Articulated Kernels for Deeper CNN Compression. - Rui Lin; Ching-Yun Ko; Zhuolun He; Cong Chen 003; Yuan Cheng; Hao Yu 001; Graziano Chesi; Ngai Wong 001 (CoRR, 2020)

DEEPEYE: A Deeply Tensor-Compressed Neural Network for Video Comprehension on Terminal Devices. - Yuan Cheng; Guangya Li; Ngai Wong 001; Hai-Bao Chen; Hao Yu 001 (ACM Trans. Embed. Comput. Syst., 2020)

Multiple-Precision Floating-Point Dot Product Unit for Efficient Convolution Computation. - Kai Li 024; Wei Mao 002; Xinang Xie; Quan Cheng; Huan Xie; Zhenjiang Dong; Hao Yu 001 (AICAS, 2021)

A Video-based Fall Detection Network by Spatio-temporal Joint-point Model on Edge Devices. - Ziyi Guan; Shuwei Li; Yuan Cheng; Changhai Man; Wei Mao 002; Ngai Wong 001; Hao Yu 001 (DATE, 2021)

A Reconfigurable Multiple-Precision Floating-Point Dot Product Unit for High-Performance Computing. - Wei Mao 002; Kai Li 024; Xinang Xie; Shirui Zhao; He Li 008; Hao Yu 001 (DATE, 2021)

Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design. - Qi Sun 002; Tinghuan Chen; Siting Liu 002; Jin Miao; Jianli Chen; Hao Yu 001; Bei Yu 001 (DATE, 2021)

An Edge-device Based Fast Fall Detection Using Spatio-temporal Optical Flow Model. - Yuchao Yang; Hongwei Ren; Chenghao Li 010; Chenchen Ding; Hao Yu 001 (EMBC, 2021)

S3-Net: A Fast and Lightweight Video Scene Understanding Network by Single-shot Segmentation. - Yuan Cheng; Yuchao Yang; Hai-Bao Chen; Ngai Wong 001; Hao Yu 001 (WACV, 2021)

Low-Power Computing with Neuromorphic Engineering. - Dingbang Liu; Hao Yu 001; Yang Chai (Adv. Intell. Syst., 2021)

Energy-Efficient and Error-Resilient Cognitive I/O for 3-D-Integrated Manycore Microprocessors. - Sai Manoj Pudukotai Dinakarrao; Hantao Huang; Hao Yu 001 (IEEE Des. Test, 2021)

TEANS: A Target Enhancement and Attenuated Nonmaximum Suppression Object Detector for Remote Sensing Images. - Hai-Bao Chen; Shan Jiang; Guanghui He; Bingyi Zhang; Hao Yu 001 (IEEE Geosci. Remote. Sens. Lett., 2021)

Fast Video Facial Expression Recognition by a Deeply Tensor-Compressed LSTM Neural Network for Mobile Devices. - Peining Zhen; Hai-Bao Chen; Yuan Cheng; Zhigang Ji; Bin Liu; Hao Yu 001 (ACM Trans. Internet Things, 2021)

S3-Net: A Fast Scene Understanding Network by Single-Shot Segmentation for Autonomous Driving. - Yuan Cheng; Yuchao Yang; Hai-Bao Chen; Ngai Wong 001; Hao Yu 001 (ACM Trans. Intell. Syst. Technol., 2021)

A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing. - Kai Li 024; Junzhuo Zhou; Boyu Li; Shuxing Yang; Sixiao Huang; Shaobo Luo; Wei Mao 002; Hao Yu 001 (AICAS, 2022)

A Low-Power Approximate Multiplier with Sign-Focus Compressor and Error Compensation. - Laimin Du; Leibin Ni; Xiong Liu; Wei Mao 002; Hao Yu 001 (APCCAS, 2022)

An Energy-Efficient Mixed-Bit ReRAM-based Computing-in-Memory CNN Accelerator with Fully Parallel Readout. - Dingbang Liu; Wei Mao 002; Haoxiang Zhou; Jun Liu; Qiuping Wu; Haiqiao Hong; Hao Yu 001 (APCCAS, 2022)

Hierarchical DNN with Heterogeneous Computing Enabled High-Performance DNA Sequencing. - Shaobo Luo; Zhiyuan Xie; Gengxin Chen; Lei Cui; Mei Yan; Xiwei Huang; Shuwei Li; Changhai Man; Wei Mao 002; Hao Yu 001 (APCCAS, 2022)

An Energy-Efficient Bit-Split-and-Combination Systolic Accelerator for NAS-Based Multi-Precision Convolution Neural Networks. - Liuyao Dai; Quan Cheng; Yuhang Wang; Gengbin Huang; Junzhuo Zhou; Kai Li 024; Wei Mao 002; Hao Yu 001 (ASP-DAC, 2022)

A Precision-Scalable Energy-Efficient Bit-Split-and-Combination Vector Systolic Accelerator for NAS-Optimized DNNs on Edge. - Kai Li 024; Junzhuo Zhou; Yuhang Wang; Junyi Luo; Zhengke Yang; Shuxin Yang; Wei Mao 002; Mingqiang Huang; Hao Yu 001 (DATE, 2022)

BaseFormer: Transformer based Base-Caller for Fast and Accurate Next Generation Sequencing. - Shuwei Li; Zhiru Guo; Ao Shen; Zheqi Yu; Wei Mao 002; Shaobo Luo; Hao Yu 001 (EMBC, 2022)

A High Throughput Multi-bit-width 3D Systolic Accelerator for NAS Optimized Deep Neural Networks on FPGA. - Mingqiang Huang; Yucen Liu; Quan Cheng; Shuxin Yang; Kai Li 024; Junyi Luo; Zhengke Yang; Qiufeng Li; Hao Yu 001; Changhai Man (FPGA, 2022)

TLCD: A Transformer based Loop Closure Detection for Robotic Visual SLAM. - Chenghao Li 010; Hongwei Ren; Minjie Bi; Chenchen Ding; Wenjie Li; Rumin Zhang; Xiaoguang Liu; Hao Yu 001 (ICARM, 2022)

FASSST: Fast Attention Based Single-Stage Segmentation Net for Real-Time Instance Segmentation. - Yuan Cheng; Rui Lin; Peining Zhen; Tianshu Hou; Chiu Wa Ng; Hai-Bao Chen; Hao Yu 001; Ngai Wong 001 (WACV, 2022)

A 703.4-GOPs/W Binary SegNet Processor With Computing-Near-Memory Architecture for Road Detection. - Haoran Lyu; Fengwei An; Shirui Zhao; Wei Mao 002; Hao Yu 001 (IEEE Des. Test, 2022)

An Energy-Efficient Mixed-Bit CNN Accelerator With Column Parallel Readout for ReRAM-Based In-Memory Computing. - Dingbang Liu; Haoxiang Zhou; Wei Mao 002; Jun Liu; Yuliang Han; Changhai Man; Qiuping Wu; Zhiru Guo; Mingqiang Huang; Shaobo Luo; Mingsong Lv; Quan Chen 007; et al. (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

ANT-UNet: Accurate and Noise-Tolerant Segmentation for Pathology Image Processing. - Yufei Chen 007; Tingtao Li; Qinming Zhang; Wei Mao 002; Nan Guan; Mei Tian; Hao Yu 001; Cheng Zhuo (ACM J. Emerg. Technol. Comput. Syst., 2022)

A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks. - Mingqiang Huang; Yucen Liu; Changhai Man; Kai Li 024; Quan Cheng; Wei Mao 002; Hao Yu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing. - Kai Li 024; Wei Mao 002; Junzhuo Zhou; Boyu Li; Zhengke Yang; Shuxing Yang; Laimin Du; Sixiao Huang; Hao Yu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design. - Qi Sun 002; Tinghuan Chen; Siting Liu 002; Jianli Chen; Hao Yu 001; Bei Yu 001 (ACM Trans. Design Autom. Electr. Syst., 2022)

An Energy-Efficient Mixed-Bitwidth Systolic Accelerator for NAS-Optimized Deep Neural Networks. - Wei Mao 002; Liuyao Dai; Kai Li 024; Quan Cheng; Yuhang Wang; Laimin Du; Shaobo Luo; Mingqiang Huang; Hao Yu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A Configurable Floating-Point Multiple-Precision Processing Element for HPC and AI Converged Computing. - Wei Mao 002; Kai Li 024; Quan Cheng; Liuyao Dai; Boyu Li; Xinang Xie; He Li 008; Longyang Lin; Hao Yu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A Fall Detection Network by 2D/3D Spatio-temporal Joint Models with Tensor Compression on Edge. - Shuwei Li; Changhai Man; Ao Shen; Ziyi Guan; Wei Mao 002; Shaobo Luo; Rumin Zhang; Hao Yu 001 (ACM Trans. Embed. Comput. Syst., 2022)

RISC-V based Fully-Parallel SRAM Computing-in-Memory Accelerator with High Hardware Utilization and Data Reuse Rate. - Haoxiang Zhou; Haiqiao Hong; Dingbang Liu; Hang Liu; Yu Xia; Kai Li 024; Jun Liu; Shaobo Luo; Wei Mao 002; Hao Yu 001 (AICAS, 2023)

Agile Hardware and Software Co-Design for RISC-V-Based Multi-Precision Deep Learning Microprocessor. - Zicheng He; Ao Shen; Qiufeng Li; Quan Cheng; Hao Yu 001 (ASP-DAC, 2023)

RankSearch: An Automatic Rank Search Towards Optimal Tensor Compression for Video LSTM Networks on Edge. - Changhai Man; Cheng Chang; Chenchen Ding; Ao Shen; Hongwei Ren; Ziyi Guan; Yuan Cheng; Shaobo Luo; Rumin Zhang; Ngai Wong 001; Hao Yu 001 (DATE, 2023)

Multi-bit-width CNN Accelerator with Systolic-in-Systolic Dataflow and Single DSP Multiple Multiplication Scheme. - Mingqiang Huang; Yucen Liu; Sixiao Huang; Kai Li 024; Qiuping Wu; Hao Yu 001 (FPGA, 2023)

TT-LCD: Tensorized-Transformer based Loop Closure Detection for Robotic Visual SLAM on Edge. - Chenchen Ding; Hongwei Ren; Zhiru Guo; Minjie Bi; Changhai Man; Tingting Wang; Shuwei Li; Shaobo Luo; Rumin Zhang; Hao Yu 001 (ICARM, 2023)

A Low-Power Sparse Convolutional Neural Network Accelerator With Pre-Encoding Radix-4 Booth Multiplier. - Quan Cheng; Liuyao Dai; Mingqiang Huang; Ao Shen; Wei Mao 002; Masanori Hashimoto; Hao Yu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Reliability Exploration of System-on-Chip With Multi-Bit-Width Accelerator for Multi-Precision Deep Neural Networks. - Quan Cheng; Mingqiang Huang; Changhai Man; Ao Shen; Liuyao Dai; Hao Yu 001; Masanori Hashimoto (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

An Integer-Only and Group-Vector Systolic Accelerator for Efficiently Mapping Vision Transformer on Edge. - Mingqiang Huang; Junyi Luo; Chenchen Ding; Zikun Wei; Sixiao Huang; Hao Yu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Novel Wideband Millimeter-Wave GaN Power Amplifier Design Using Transistors With Large Drain Capacitance and High Optimum Load Impedance. - Jie Shi; Xiaohu Fang; Hao Yu 001; Jiangwei Sui; Kwok-Keung Michael Cheng (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 13-34 TOPS/W Edge-AI Processor Featuring Booth-Value-Confined Accelerator, Near-Memory Computing, and Contiguity-Aware Mapping. - Quan Cheng; Longyang Lin; Mingqiang Huang; Qiufeng Li; Zhengke Yang; Liuyao Dai; Hao Yu 001; Yu-Jen Chen; Yiyu Shi 001; Masanori Hashimoto (A-SSCC, 2024)

A 29.12 TOPS/W and 1.13 TOPS/mm2 NAS-Optimized Mixed-Precision DNN Accelerator with Vector Split- and-Combination Systolic in 28nm CMOS. - Kai Li 024; Hantao Huang; Mingqiang Huang; Chenchen Ding; Longyang Lin; Liebing Ni; Hao Yu 001 (CICC, 2024)

How accurately can soft error impact be estimated in black-box/white-box cases? - a case study with an edge AI SoC -. - Quan Cheng; Qiufeng Li; Longyang Lin; Wang Liao; Liuyao Dai; Hao Yu 001; Masanori Hashimoto (DAC, 2024)

APTQ: Attention-aware Post-Training Mixed-Precision Quantization for Large Language Models. - Ziyi Guan; Hantao Huang; Yupeng Su; Hong Huang; Ngai Wong 001; Hao Yu 001 (DAC, 2024)

An Isotropic Shift-Pointwise Network for Crossbar-Efficient Neural Network Design. - Ziyi Guan; Boyu Li; Yuan Ren; Muqun Niu; Hantao Huang; Graziano Chesi; Hao Yu 001; Ngai Wong 001 (DATE, 2024)

FMTT: Fused Multi-Head Transformer with Tensor-Compression for 3D Point Clouds Detection on Edge Devices. - Zikun Wei; Tingting Wang; Chenchen Ding; Bohan Wang; Ziyi Guan; Hantao Huang; Hao Yu 001 (DATE, 2024)

LAMPS: A Layer-wised Mixed-Precision-and-Sparsity Accelerator for NAS-Optimized CNNs on FPGA. - Shuxin Yang; Chenchen Ding; Mingqiang Huang; Kai Li 024; Chenghao Li 010; Zikun Wei; Sixiao Huang; Jingyao Dong; Liuyang Zhang; Hao Yu 001 (FCCM, 2024)

Rethinking Efficient and Effective Point-based Networks for Event Camera Classification and Regression: EventMamba. - Hongwei Ren; Yue Zhou 010; Jiadong Zhu; Haotian Fu; Yulong Huang; Xiaopeng Lin; Yuetong Fang; Fei Ma 006; Hao Yu 001; Bojun Cheng (CoRR, 2024)

EdgeLLM: A Highly Efficient CPU-FPGA Heterogeneous Edge Accelerator for Large Language Models. - Mingqiang Huang; Ao Shen; Kai Li 024; Haoxiang Peng; Boyu Li; Hao Yu 001 (CoRR, 2024)

LLM-Barber: Block-Aware Rebuilder for Sparsity Mask in One-Shot for Large Language Models. - Yupeng Su; Ziyi Guan; Xiaoqun Liu; Tianlai Jin; Dongkuan Wu; Graziano Chesi; Ngai Wong 001; Hao Yu 001 (CoRR, 2024)

A Low-Power DNN Accelerator With Mean-Error-Minimized Approximate Signed Multiplier. - Laimin Du; Leibin Ni; Xiong Liu; Guanqi Peng; Kai Li 024; Wei Mao 002; Hao Yu 001 (IEEE Open J. Circuits Syst., 2024)

A Reconfigurable Processing Element for Multiple-Precision Floating/Fixed-Point HPC. - Boyu Li; Kai Li 024; Jiajun Zhou; Yuan Ren; Wei Mao 002; Hao Yu 001; Ngai Wong 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Low-Power Charge-Domain Bit-Scalable Readout System for Fully-Parallel Computing-in-Memory Accelerators. - Wei Mao 002; Fuyi Li; Jun Liu; Rui Xiao; Kejie Huang; Yongfu Li 002; Hao Yu 001; Yan Liu 016; Genquan Han (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Layer-wised Mixed-Precision CIM Accelerator with Bit-level Sparsity-aware ADCs for NAS-Optimized CNNs. - Haoxiang Zhou; Zikun Wei; Dingbang Liu; Liuyang Zhang; Chenchen Ding; Jiaqi Yang; Wei Mao 002; Hao Yu 001 (ASP-DAC, 2025)

Fast Routing Algorithm for Mask Stitching Region of Ultra Large Wafer Scale Integration. - Zhen Zhuang; Quan Chen 007; Hao Yu 001; Tsung-Yi Ho (ASP-DAC, 2025)

A 22nm Resource-Frugal Hyper-Heterogeneous Multi-Modal System-on-Chip Towards In-Orbit Computing. - Quan Cheng; Qiufeng Li; Weirong Dong; Mingtao Zhang; Ruilin Zhang; Mingqiang Huang; Hao Yu 001; Yiyu Shi 001; Hiromitsu Awano; Takashi Sato 001; Longyang Lin; Masanori Hashimoto (CICC, 2025)

A 22nm 29.3TOPS/W End-to-End CIM-Utilization-Aware Accelerator with Reconfigurable 4D-CIM Mapping and Adaptive Feature Reuse for Diverse CNNs and Transformers. - Jin Wang; Moxiao Lou; Zhengke Yang; Ruijie Peng; Humiao Li; Weirong Dong; Haoran Lyu; Yida Li; Jiamin Li; Hao Yu 001; Jerald Yoo; Longyang Lin (CICC, 2025)

HachiFI: A Lightweight SoC Architecture-Independent Fault-Injection Framework for SEU Impact Evaluation. - Quan Cheng; Wang Liao; Ruilin Zhang; Hao Yu 001; Longyang Lin; Masanori Hashimoto (DATE, 2025)

EdgeLLM: A Highly Efficient CPU-FPGA Heterogeneous Edge Accelerator for Large Language Models. - Mingqiang Huang; Ao Shen; Kai Li 024; Haoxiang Peng; Boyu Li; Yupeng Su; Hao Yu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A 28-nm 135.19 TOPS/W Bootstrapped-SRAM Compute-in-Memory Accelerator With Layer-Wise Precision and Sparsity. - Wei Mao 002; Dingbang Liu; Haoxiang Zhou; Fuyi Li; Kai Li 024; Qiuping Wu; Jiaqi Yang; Quan Cheng; Liuyang Zhang; Hao Yu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

Rethinking Efficient and Effective Point-Based Networks for Event Camera Classification and Regression. - Hongwei Ren; Yue Zhou 010; Jiadong Zhu; Xiaopeng Lin; Haotian Fu; Yulong Huang; Yuetong Fang; Fei Ma 006; Hao Yu 001; Bojun Cheng (IEEE Trans. Pattern Anal. Mach. Intell., 2025)