A 0.2V 2.3pJ/Cycle 28dB output SNR hybrid Markov random field probabilistic-based circuit for noise immunity and energy efficiency. - Xuwei Jin; Wei Jin 004; Hao Zhang 151; Jianfei Jiang 001; Weifeng He (ISCAS, 2017)

An Area-Efficient Scannable In Situ Timing Error Detection Technique Featuring Low Test Overhead for Resilient Circuits. - Hao Zhang 151; Weifeng He; Yanan Sun 003; Mingoo Seok (ICCAD, 2021)

Investigation of Dynamic Leakage-Suppression Logic Techniques Crossing Different Technology Nodes from 180 nm Bulk CMOS to 7 nm FinFET Plus Process. - Jieyu Li; Zihan Lian; Hao Zhang 151; Weifeng He; Yanan Sun 003; Mingoo Seok (ISCAS, 2021)

An Energy-Efficient Logic Cell Library Design Methodology with Fine Granularity of Driving Strength for Near- and Sub-Threshold Digital Circuits. - Hao Zhang 151; Weifeng He; Yanan Sun 003; Mingoo Seok (ISCAS, 2021)

An Ultra-Low Leakage Bitcell Structure with the Feedforward Self-Suppression Scheme for Near-Threshold SRAM. - Hao Zhang 151; Jieyu Li; Weifeng He; Yanan Sun 003; Mingoo Seok (ISCAS, 2021)

A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead. - Hao Zhang 151; Weifeng He; Yanan Sun 003; Mingoo Seok (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A 12-nm High-Density Energy-Efficient 1-Mb 2R2W Scratchpad With Local Blocks for Neural Network Applications. - Hao Zhang 151; Weifeng He; Wim Dehaene (IEEE J. Solid State Circuits, 2025)