EZ-Pass: An Energy & Performance-Efficient Power-Gating Router Architecture for Scalable NoCs. - Hao Zheng 005; Ahmed Louri (IEEE Comput. Archit. Lett., 2018)

An Energy-Efficient Network-on-Chip Design using Reinforcement Learning. - Hao Zheng 005; Ahmed Louri (DAC, 2019)

A Versatile and Flexible Chiplet-based System Design for Heterogeneous Manycore Architectures. - Hao Zheng 005; Ke Wang 030; Ahmed Louri (DAC, 2020)

TSA-NoC: Learning-Based Threat Detection and Mitigation for Secure Network-on-Chip Architecture. - Ke Wang 030; Hao Zheng 005; Ahmed Louri (IEEE Micro, 2020)

Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore Architectures. - Hao Zheng 005; Ke Wang 030; Ahmed Louri (HPCA, 2021)

AGAPE: Anomaly Detection with Generative Adversarial Network for Improved Performance, Energy, and Security in Manycore Systems. - Ke Wang 030; Hao Zheng 005; Yuan Li 029; Jiajun Li; Ahmed Louri (DATE, 2022)

Adapt-Flow: A Flexible DNN Accelerator Architecture for Heterogeneous Dataflow Implementation. - Jiaqi Yang; Hao Zheng 005; Ahmed Louri (ACM Great Lakes Symposium on VLSI, 2022)

Ascend: A Scalable and Energy-Efficient Deep Neural Network Accelerator With Photonic Interconnects. - Yuan Li 029; Ke Wang 030; Hao Zheng 005; Ahmed Louri; Avinash Karanth (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Agile: A Learning-Enabled Power and Performance-Efficient Network-on-Chip Design. - Hao Zheng 005; Ahmed Louri (IEEE Trans. Emerg. Top. Comput., 2022)

SGCNAX: A Scalable Graph Convolutional Neural Network Accelerator With Workload Balancing. - Jiajun Li; Hao Zheng 005; Ke Wang 030; Ahmed Louri (IEEE Trans. Parallel Distributed Syst., 2022)

SecureNoC: A Learning-Enabled, High-Performance, Energy-Efficient, and Secure On-Chip Communication Framework Design. - Ke Wang 030; Hao Zheng 005; Yuan Li 029; Ahmed Louri (IEEE Trans. Sustain. Comput., 2022)

Venus: A Versatile Deep Neural Network Accelerator Architecture Design for Multiple Applications. - Jiaqi Yang; Hao Zheng 005; Ahmed Louri (DAC, 2023)

OCMGen: Extended Design Space Exploration with Efficient FPGA Memory Inference. - Sanjay Gandham; Lingxiang Yin; Hao Zheng 005; Mingjie Lin (FCCM, 2023)

Exploring Architecture, Dataflow, and Sparsity for GCN Accelerators: A Holistic Framework. - Lingxiang Yin; Jun Wang 001; Hao Zheng 005 (ACM Great Lakes Symposium on VLSI, 2023)

SAGA: Sparsity-Agnostic Graph Convolutional Network Acceleration with Near-Optimal Workload Balance. - Sanjay Gandham; Lingxiang Yin; Hao Zheng 005; Mingjie Lin (ICCAD, 2023)

Path-Based Processing using In-Memory Systolic Arrays for Accelerating Data-Intensive Applications. - Muhammad Rashedul Haq Rashed; Sven Thijssen; Sumit Kumar Jha 001; Hao Zheng 005; Rickard Ewetz (ICCAD, 2023)

ARIES: Accelerating Distributed Training in Chiplet-Based Systems via Flexible Interconnects. - Lingxiang Yin; Amir Ghazizadeh; Ahmed Louri; Hao Zheng 005 (ICCAD, 2023)

Polyform: A Versatile Architecture for Multi-DNN Execution via Spatial and Temporal Acceleration. - Lingxiang Yin; Amir Ghazizadeh; Shilin Tian; Ahmed Louri; Hao Zheng 005 (ICCD, 2023)

FDMAX: An Elastic Accelerator Architecture for Solving Partial Differential Equations. - Jiajun Li; Yuxuan Zhang; Hao Zheng 005; Ke Wang 030 (ISCA, 2023)

GShuttle: Optimizing Memory Access Efficiency for Graph Convolutional Neural Network Accelerators. - Jiajun Li; Ke Wang 030; Hao Zheng 005; Ahmed Louri (J. Comput. Sci. Technol., 2023)

Towards Area-Efficient Path-Based In-Memory Computing using Graph Isomorphisms. - Sven Thijssen; Muhammad Rashedul Haq Rashed; Hao Zheng 005; Sumit Kumar Jha 001; Rickard Ewetz (ASPDAC, 2024)

VITA: ViT Acceleration for Efficient 3D Human Mesh Recovery via Hardware-Algorithm Co-Design. - Shilin Tian; Chase Szafranski; Ce Zheng; Fan Yao; Ahmed Louri; Chen Chen 001; Hao Zheng 005 (DAC, 2024)

EGMA: Enhancing Data Reuse and Workload Balancing in Message Passing GNN Acceleration via Gram Matrix Optimization. - Fangzhou Ye; Lingxiang Yin; Amir Ghazizadeh Ahsaei; Hao Zheng 005 (DAC, 2024)

CircuitSeer: RTL Post-PnR Delay Prediction via Coupling Functional and Structural Representation. - Sanjay Gandham; Joe Walston; Sourav Samanta; Lingxiang Yin; Hao Zheng 005; Mingjie Lin; Stelios Diamantidis (ICCAD, 2024)

Aurora: A Versatile and Flexible Accelerator for Graph Neural Networks. - Jiaqi Yang; Hao Zheng 005; Ahmed Louri (IPDPS, 2024)

MetaLeak: Uncovering Side Channels in Secure Processor Architectures Exploiting Metadata. - Md Hafizul Islam Chowdhuryy; Hao Zheng 005; Fan Yao (ISCA, 2024)

CryptoTrain: Fast Secure Training on Encrypted Dataset. - Jiaqi Xue; Yancheng Zhang; Yanshan Wang; Xueqiang Wang; Hao Zheng 005; Qian Lou (LAMPS@CCS, 2024)

SCALE: A Structure-Centric Accelerator for Message Passing Graph Neural Networks. - Lingxiang Yin; Sanjay Gandham; Mingjie Lin; Hao Zheng 005 (MICRO, 2024)

Morph-GCNX: A Universal Architecture for High-Performance and Energy-Efficient Graph Convolutional Network Acceleration. - Ke Wang 030; Hao Zheng 005; Jiajun Li; Ahmed Louri (IEEE Trans. Sustain. Comput., 2024)

Versa-DNN: A Versatile Architecture Enabling High-Performance and Energy-Efficient Multi-DNN Acceleration. - Jiaqi Yang; Hao Zheng 005; Ahmed Louri (IEEE Trans. Parallel Distributed Syst., 2024)

I-DGNN: A Graph Dissimilarity-based Framework for Designing Scalable and Efficient DGNN Accelerators. - Jiaqi Yang; Hao Zheng 005; Ahmed Louri (HPCA, 2025)

DiTile-DGNN: An Efficient Accelerator for Distributed Dynamic Graph Neural Network Inference. - Jiaqi Yang; Hao Zheng 005; Ahmed Louri (ISCA, 2025)