Hao Zhou

According to our database, Hao Zhou authored at least 28 papers between 2011 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

An Efficient Reinforcement Learning Based Framework for Exploring Logic Synthesis.

Yu Qian, Xuegong Zhou, Hao Zhou, Lingli Wang

ACM Trans. Design Autom. Electr. Syst., March, 2024

2023

An Optimized GIB Routing Architecture with Bent Wires for FPGA.

Kaichuang Shi, Xuegong Zhou, Hao Zhou, Lingli Wang

ACM Trans. Reconfigurable Technol. Syst., March, 2023

FET-OPU: A Flexible and Efficient FPGA-Based Overlay Processor for Transformer Networks.

Yueyin Bai, Hao Zhou, Keqing Zhao, Hongji Wang, Jianli Chen, Jun Yu, Kun Wang

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

g-BERT: Enabling Green BERT Deployment on FPGA via Hardware-Aware Hybrid Pruning.

Yueyin Bai, Hao Zhou, Ruiqi Chen, Kuangjie Zou, Jialin Cao, Haoyang Zhang, Jianli Chen, Jun Yu, Kun Wang

Proceedings of the IEEE International Conference on Communications, 2023

Explore the Feedback Interconnects in Intra-Cluster Routing for FPGAs.

Kaichuang Shi, Hao Zhou, Lingli Wang

Proceedings of the International Conference on Field Programmable Technology, 2023

VIB: A Versatile Interconnection Block for FPGA Routing Architecture.

Kaichuang Shi, Hao Zhou, Lingli Wang

Proceedings of the International Conference on Field Programmable Technology, 2023

AMG: Automated Efficient Approximate Multiplier Generator for FPGAs via Bayesian Optimization.

Zhen Li, Hao Zhou, Lingli Wang, Xuegong Zhou

Proceedings of the International Conference on Field Programmable Technology, 2023

LTrans-OPU: A Low-Latency FPGA-Based Overlay Processor for Transformer Networks.

Yueyin Bai, Hao Zhou, Keqing Zhao, Manting Zhang, Jianli Chen, Jun Yu, Kun Wang

Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

Transformer-OPU: An FPGA-based Overlay Processor for Transformer Networks.

Yueyin Bai, Hao Zhou, Keqing Zhao, Jianli Chen, Jun Yu, Kun Wang

Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

Efficient FPGA Routing Architecture Exploration Based on Two-Stage MUXes.

Jide Zhang, Kaixiang Zhu, Kaichuang Shi, Lingli Wang, Hao Zhou

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022

Efficient Reinforcement Learning Framework for Automated Logic Synthesis Exploration.

Yu Qian, Xuegong Zhou, Hao Zhou, Lingli Wang

Proceedings of the International Conference on Field-Programmable Technology, 2022

GRAEBO: FPGA General Routing Architecture Exploration via Bayesian Optimization.

Su Zheng, Jiadong Qian, Hao Zhou, Lingli Wang

Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

2021

A novel DC-DC converter and LDO cascaded circuit with improved dynamic response and loop stability.

Hao Zhou, Hao Min, Ping Luo

IEICE Electron. Express, 2021

A Hexagon-Based Honeycomb Routing Architecture for FPGA.

Kaichuang Shi, Hao Zhou, Lingli Wang

Proceedings of the International Conference on Field-Programmable Technology, 2021

General routing architecture modelling and exploration for modern FPGAs.

Jiadong Qian, Yuhang Shen, Kaichuang Shi, Hao Zhou, Lingli Wang

Proceedings of the International Conference on Field-Programmable Technology, 2021

APIR-DSP: An approximate PIR-DSP architecture for error-tolerant applications.

Yuan Dai, Simin Liu, Yao Lu, Hao Zhou, Seyedramin Rasoulinezhad, Philip H. W. Leong, Lingli Wang

Proceedings of the International Conference on Field-Programmable Technology, 2021

Two-level MUX Design and Exploration in FPGA Routing Architecture.

Yuhang Shen, Jiadong Qian, Kaichuang Shi, Lingli Wang, Hao Zhou

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

2020

GIB: A Novel Unidirectional Interconnection Architecture for FPGA.

Kaichuang Shi, Hao Zhou, Xuegong Zhou, Lingli Wang

Proceedings of the International Conference on Field-Programmable Technology, 2020

LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations.

Seyedramin Rasoulinezhad, Siddhartha, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

2019

MajorityNets: BNNs Utilising Approximate Popcount for Improved Efficiency.

Seyedramin Rasoulinezhad, Sean Fox, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong

Proceedings of the International Conference on Field-Programmable Technology, 2019

Bent Routing Pattern for FPGA.

Xibo Sun, Hao Zhou, Lingli Wang

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

PIR-DSP: An FPGA DSP Block Architecture for Multi-precision Deep Neural Networks.

Seyedramin Rasoulinezhad, Hao Zhou, Lingli Wang, Philip H. W. Leong

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2018

Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element Method.

Hao Zhou, Hengliang Zhu, Tao Cui, David Z. Pan, Dian Zhou, Xuan Zeng

IEEE Trans. Very Large Scale Integr. Syst., 2018

Interlayer Cooling Network Design for High-Performance 3D ICs Using Channel Patterning and Pruning.

Hengliang Zhu, Feng Hu, Hao Zhou, David Z. Pan, Dian Zhou, Xuan Zeng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017

A fast HDL model for full-custom FPGA verification.

Kaixuan Zhang, Zhihua Feng, Hao Zhou

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2015

An 8-bit 4fs-step digitally controlled delay element with two cascaded delay units.

Weizhen Wang, Hao Zhou, Fan Ye, Junyan Ren

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2013

Power efficient SAR ADC with optimized settling technique.

Weiru Gu, Hao Zhou, Tao Lin, Zhenyu Wang, Fan Ye, Junyan Ren

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

2011

FPGA interconnect timing library based on the statistical method.

Xiangzhi Meng, Liguang Chen, Hao Zhou, Jian Wang, Meng Yang, Jinmei Lai

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011