FPGA interconnect timing library based on the statistical method. - Xiangzhi Meng; Liguang Chen; Hao Zhou 008; Jian Wang 036; Meng Yang 013; Jinmei Lai 001 (ASICON, 2011)

FPGA bitstream compression and decompression using LZ and golomb coding (abstract only). - Jinsong Mao; Hao Zhou 008; Haijiang Ye; Jinmei Lai 001 (FPGA, 2013)

Power efficient SAR ADC with optimized settling technique. - Weiru Gu; Hao Zhou 008; Tao Lin; Zhenyu Wang; Fan Ye 001; Junyan Ren (MWSCAS, 2013)

An 8-bit 4fs-step digitally controlled delay element with two cascaded delay units. - Weizhen Wang; Hao Zhou 008; Fan Ye 001; Junyan Ren (ASICON, 2015)

A fast HDL model for full-custom FPGA verification. - Kaixuan Zhang; Zhihua Feng; Hao Zhou 008 (ASICON, 2017)

Interlayer Cooling Network Design for High-Performance 3D ICs Using Channel Patterning and Pruning. - Hengliang Zhu; Feng Hu; Hao Zhou 008; David Z. Pan; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element Method. - Hao Zhou 008; Hengliang Zhu; Tao Cui; David Z. Pan; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

PIR-DSP: An FPGA DSP Block Architecture for Multi-precision Deep Neural Networks. - Seyedramin Rasoulinezhad; Hao Zhou 008; Lingli Wang; Philip H. W. Leong (FCCM, 2019)

Bent Routing Pattern for FPGA. - Xibo Sun; Hao Zhou 008; Lingli Wang (FPL, 2019)

MajorityNets: BNNs Utilising Approximate Popcount for Improved Efficiency. - Seyedramin Rasoulinezhad; Sean Fox; Hao Zhou 008; Lingli Wang; David Boland; Philip H. W. Leong (FPT, 2019)

LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations. - Seyedramin Rasoulinezhad; Siddhartha 003; Hao Zhou 008; Lingli Wang; David Boland; Philip H. W. Leong (FPGA, 2020)

GIB: A Novel Unidirectional Interconnection Architecture for FPGA. - Kaichuang Shi; Hao Zhou 008; Xuegong Zhou; Lingli Wang (FPT, 2020)

Two-level MUX Design and Exploration in FPGA Routing Architecture. - Yuhang Shen; Jiadong Qian; Kaichuang Shi; Lingli Wang; Hao Zhou 008 (FPL, 2021)

APIR-DSP: An approximate PIR-DSP architecture for error-tolerant applications. - Yuan Dai; Simin Liu; Yao Lu; Hao Zhou 008; Seyedramin Rasoulinezhad; Philip H. W. Leong; Lingli Wang (FPT, 2021)

General routing architecture modelling and exploration for modern FPGAs. - Jiadong Qian; Yuhang Shen; Kaichuang Shi; Hao Zhou 008; Lingli Wang (FPT, 2021)

A Hexagon-Based Honeycomb Routing Architecture for FPGA. - Kaichuang Shi; Hao Zhou 008; Lingli Wang (FPT, 2021)

A novel DC-DC converter and LDO cascaded circuit with improved dynamic response and loop stability. - Hao Zhou 008; Hao Min; Ping Luo (IEICE Electron. Express, 2021)

GRAEBO: FPGA General Routing Architecture Exploration via Bayesian Optimization. - Su Zheng; Jiadong Qian; Hao Zhou 008; Lingli Wang (FPL, 2022)

Efficient Reinforcement Learning Framework for Automated Logic Synthesis Exploration. - Yu Qian; Xuegong Zhou; Hao Zhou 008; Lingli Wang (FPT, 2022)

Efficient FPGA Routing Architecture Exploration Based on Two-Stage MUXes. - Jide Zhang; Kaixiang Zhu; Kaichuang Shi; Lingli Wang; Hao Zhou 008 (ASICON, 2023)

Transformer-OPU: An FPGA-based Overlay Processor for Transformer Networks. - Yueyin Bai; Hao Zhou 008; Keqing Zhao; Jianli Chen; Jun Yu 010; Kun Wang 005 (FCCM, 2023)

LTrans-OPU: A Low-Latency FPGA-Based Overlay Processor for Transformer Networks. - Yueyin Bai; Hao Zhou 008; Keqing Zhao; Manting Zhang; Jianli Chen; Jun Yu 010; Kun Wang 005 (FPL, 2023)

AMG: Automated Efficient Approximate Multiplier Generator for FPGAs via Bayesian Optimization. - Zhen Li; Hao Zhou 008; Lingli Wang; Xuegong Zhou (ICFPT, 2023)

VIB: A Versatile Interconnection Block for FPGA Routing Architecture. - Kaichuang Shi; Hao Zhou 008; Lingli Wang (ICFPT, 2023)

Explore the Feedback Interconnects in Intra-Cluster Routing for FPGAs. - Kaichuang Shi; Hao Zhou 008; Lingli Wang (ICFPT, 2023)

g-BERT: Enabling Green BERT Deployment on FPGA via Hardware-Aware Hybrid Pruning. - Yueyin Bai; Hao Zhou 008; Ruiqi Chen 001; Kuangjie Zou; Jialin Cao; Haoyang Zhang; Jianli Chen; Jun Yu 010; Kun Wang 005 (ICC, 2023)

FET-OPU: A Flexible and Efficient FPGA-Based Overlay Processor for Transformer Networks. - Yueyin Bai; Hao Zhou 008; Keqing Zhao; Hongji Wang; Jianli Chen; Jun Yu 010; Kun Wang 005 (ICCAD, 2023)

An Optimized GIB Routing Architecture with Bent Wires for FPGA. - Kaichuang Shi; Xuegong Zhou; Hao Zhou 008; Lingli Wang (ACM Trans. Reconfigurable Technol. Syst., 2023)

CSTrans-OPU: An FPGA-based Overlay Processor with Full Compilation for Transformer Networks via Sparsity Exploration. - Yueyin Bai; Keqing Zhao; Yang Liu 376; Hongji Wang; Hao Zhou 008; Xiaoxing Wu; Jun Yu 010; Kun Wang 005 (DAC, 2024)

SDAcc: A Stable Diffusion Accelerator on FPGA via Software-Hardware Co-Design. - Hao Zhou 008; Yang Liu 376; Hongji Wang; Enhao Tang; Shun Li; Yifan Zhang; Kun Wang 005 (FCCM, 2024)

An Efficient Reinforcement Learning Based Framework for Exploring Logic Synthesis. - Yu Qian; Xuegong Zhou; Hao Zhou 008; Lingli Wang (ACM Trans. Design Autom. Electr. Syst., 2024)

Graph-OPU: A Highly Flexible FPGA-Based Overlay Processor for Graph Neural Networks. - Enhao Tang; Shun Li; Ruiqi Chen 001; Hao Zhou 008; Yuhanxiao Ma; Haoyang Zhang; Jun Yu 010; Kun Wang 005 (ACM Trans. Reconfigurable Technol. Syst., 2024)

Deploying Diffusion Models with Scheduling Space Search and Memory Overflow Prevention Based on Graph Optimization. - Hao Zhou 008; Yang Liu 376; Hongji Wang; Enhao Tang; Shun Li; Yifan Zhang; Guohao Dai; Yongpan Liu; Kun Wang 005 (ASP-DAC, 2025)

D-GCN: A Dynamic Pruning Accelerator for Deep Graph Convolutional Networks with Hybrid Dataflow. - Shun Li; Hao Zhou 008; Enhao Tang; Yang Liu 376; Shidi Tang; Ming Ling (ACM Great Lakes Symposium on VLSI, 2025)