Energy-Efficient Switching Scheme with 93.41% Reduction in Capacitor Area for SAR ADC. - Shubin Liu; Haolin Han; Ruixue Ding (J. Circuits Syst. Comput., 2019)

A 12-Bit 100-MS/s Pipelined-SAR ADC With PVT-Insensitive and Gain-Folding Dynamic Amplifier. - Shubin Liu; Haolin Han; Yi Shen 007; Zhangming Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A 0.012mm2 36.41kHz Temperature-insensitive Current-Reuse Ring Oscillator Achieving 0.077%/V Line Sensitivity across a 1.3V-to-3.7V unregulated Supply. - Zhicheng Dong; Shubin Liu; Xiaoteng Zhao; Baotian Hao; Hongzhi Liang; Haolin Han; Menghao Wang; Weijie Han; Zhangming Zhu (CICC, 2023)

A 12b 1.5GS/s Single-Channel Pipelined SAR ADC with a Pipelined Residue Amplification Stage. - Yi Shen 007; Shubin Liu; Yue Cao; Haolin Han; Hongzhi Liang; Zhicheng Dong; Dengquan Li; Ruixue Ding; Zhangming Zhu (CICC, 2023)

A 0.0006-mm2 0.13-pJ/bit 9-21-Gb/s Sampling CDR with Inverter-Based Frequency Multiplier and Embedded 1: 3 DEMUX in 65-nm CMOS. - Zhicheng Dong; Xiaoteng Zhao; Zekai Yang; Xianting Su; Haolin Han; Feng Bu; Rong Zhou; Depeng Sun; Yong Chen 005; Shubin Liu; Ruixue Ding; Zhangming Zhu (A-SSCC, 2024)

A wide load-range OTA using a digitally assisted compensating technique. - Haolin Han; Shubin Liu; Yi Shen 007; Hongzhi Liang; Yue Cao; Longjie Zhong; Zhangming Zhu (Sci. China Inf. Sci., 2024)

A 68.5 dB-SNDR, 12.4-fJ/conv.-step, 100-MS/s pipelined-SAR ADC with PVT-enhanced circuitry. - Haolin Han; Ruili Ren; Yi Shen 007; Ruixue Ding; Shubin Liu; Hongzhi Liang (Microelectron. J., 2024)

A PVT-robust Gm-R-based residue amplifier with folded positive feedback technique. - Haolin Han; Jinwei Zhang; Ruili Ren; Yi Shen 007; Shubin Liu; Ruixue Ding (Microelectron. J., 2024)

A Power-Efficient Clock Circuit and Output Serializing Technique Integrated in a 12-bit 10-GS/s ADC. - Haolin Han; Shubin Liu; Hongzhi Liang; Yi Shen 007; Jianyu Guo; Ruili Ren; Zhangming Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 32GS/s 8b 16× Time-Interleaved Hybrid ADC with Self-Detection Offset Calibration, DLL-Based TLSB PVT Variation Calibration and VTC Gain Self-Tracking. - Hongzhi Liang; Jun Chang; Yixiao Luo; Zeyu Peng; Weimin Zhou; Li Dang; Yue Cao; Haolin Han; Yi Shen 007; Shubin Liu; Ruixue Ding; Zhangming Zhu (CICC, 2025)

24.2 A 14b 1GS/s Single-Channel Pipelined ADC with A Parallel-Operation SAR Sub-Quantizer and A Dynamic-Deadzone Ring Amplifier. - Yue Cao; Yi Shen 007; Shubin Liu; Haolin Han; Hongzhi Liang; Li Dang; Dengquan Li; Ruixue Ding; Zhangming Zhu (ISSCC, 2025)

Rapid digital background calibration of bit weights in pipelined SAR ADC based on multi-PN injection. - Le Chen; Yi Shen 007; Ruixue Ding; Shubin Liu; Haolin Han (Microelectron. J., 2025)

A linearized PVT-robust FVF input buffer with triode transconductance feedback achieving SFDR > 90 dB at 500-MHz input. - Junye Su; Shubin Liu; Haolin Han (Microelectron. J., 2025)

A 12-bit 1.5-GS/s Single-Channel Pipelined SAR ADC With a Pipelined Residue Amplification Stage. - Yi Shen 007; Shubin Liu; Yue Cao; Haolin Han; Hongzhi Liang; Zhicheng Dong; Dengquan Li; Ruixue Ding; Zhangming Zhu (IEEE J. Solid State Circuits, 2025)

Metastable-Dither-Based Digital Background Calibration of Interstage Gain Nonlinearity in Pipelined SAR ADC. - Le Chen; Yue Cao; Lin Ling; Shubin Liu; Haolin Han (IEEE Trans. Very Large Scale Integr. Syst., 2025)