A data compression technique based on reversed leading bits coding and Huffman coding. - Haoqi Ren (ChinaCom, 2015)

A VLIW DSP for communication applications. - Haoqi Ren; Zhifeng Zhang 001; Jun Wu 006 (IGSC, 2015)

An ASIC Fast Decoder of Rate Compatible Modulation and Its Application in Wireless Communication System. - Wei Yu; Jun Wu 006; Hao Cui 001; Zhifeng Zhang 001; Haoqi Ren (MLICOM, 2016)

SWIFT: A Computationally-Intensive DSP Architecture for Communication Applications. - Haoqi Ren; Zhifeng Zhang 001; Jun Wu 006 (Mob. Networks Appl., 2016)

Domain specific compiler for coordinated signal processing in 5G testbed. - Han Li; Haoqi Ren; Jun Wu 006 (SmartIoT@SEC, 2017)

A compilation method for zero overhead loop in DSPs with VLIW. - Rui Chang; Jun Wu 006; Haoqi Ren (WCSP, 2017)

基于跳转轨迹的分支目标缓冲研究 (Efficient BTB Based on Taken Trace). - Zhenya Xiong; Zhenghao Lin; Haoqi Ren (计算机科学, 2017)

DSP Implementation and Optimization of Pseudo Analog Video Transmission Algorithm. - Chengcheng Wang; Pengfei Xia; Haoqi Ren; Jun Wu 006; Zhifeng Zhang 001 (ChinaCom, 2018)

Design and Implementation of Assembler for High Performance Digital Signal Processor (DSP). - Peng Ding; Haoqi Ren; Zhifeng Zhang 001; Jun Wu 006; Fusheng Zhu; Wenru Zhang (ChinaCom (1), 2019)

Hardware Implementation of a Pseudo-Analog Wireless Video Transmission System. - Shi Chen; Jun Wu 006; Haoqi Ren; Jian Wu; Baoye Zhang; Fusheng Zhu (ICCT, 2019)

A High-Performance Systolic Array Accelerator Dedicated for CNN. - Jing Shen; Haoqi Ren; Zhifeng Zhang 001; Jun Wu 006; Wenqi Pan; Zhenyu Jiang (ICCT, 2019)

Reinforcement Learning Based Wireless Augmented Reality on Mobile Edge Computing. - Rui Qin; Dian Liu; Jun Wu 006; Fusheng Zhu; Haoqi Ren; Zhifeng Zhang 001 (ICII, 2019)

HARQ-Chaotic: Analog Chaotic Code Applied in HARQ Scheme of Wireless Communication System. - Wei Yu; Fusheng Zhu; Jun Wu 006; Rui Wang 001; Haoqi Ren; Zhifeng Zhang 001 (Wirel. Commun. Mob. Comput., 2019)

Efficient Architecture for Convolution and Softmax Function in Deep Learning Accelerator. - Zhenyu Jiang; Zhifeng Zhang 001; Haoqi Ren; Jun Wu 006 (ChinaCom, 2020)

A Deep Learning Compiler for Vector Processor. - Pingping Pan; Jun Wu 006; Songyuan Zhao; Haoqi Ren; Zhifeng Zhang 001 (ChinaCom, 2020)

A Real-time Virtual Reality Adaptive Streaming System. - Songyuan Zhao; Bin Tan; Jun Wu 006; Haoqi Ren; Zhifeng Zhang 001 (VTC Fall, 2020)

Reinforcement Learning-Based Optimal Computing and Caching in Mobile Edge Network. - Yichen Qian; Rui Wang 001; Jun Wu 006; Bin Tan; Haoqi Ren (IEEE J. Sel. Areas Commun., 2020)

Design and Verification of High Performance Memory Interface Based on AXI Bus. - Ming Chen; Zhifeng Zhang 001; Haoqi Ren (ICCT, 2021)

Design and Implementation of DSP Cache. - Kunkun Liang; Jun Wu 006; Haoqi Ren; Zhifeng Zhang 001; Bin Tan (ICCT, 2021)

A Blockchain Based Automatic Access Scheme Design and Implement for Small Cell Base Station. - Jingchao Liang; Jun Wu 006; Bin Tan; Haoqi Ren; Zhifeng Zhang 001 (ICCT, 2021)

DSP Assembler Auto-Generation Technique and ToolChain Integration. - Wanli Wang; Jun Wu 006; Haoqi Ren; Zhifeng Zhang 001 (ICCT, 2021)

Cache Placement Optimization in Mobile Edge Computing Networks with Unaware Environment - An Extended Multi-armed Bandit Approach. - Yuqi Han; Rui Wang 001; Jun Wu 006; Dian Liu; Haoqi Ren (CoRR, 2021)

A Deep Image Coding Scheme With Generative Network to Learn From Correlated Images. - Yihao Chen; Bin Tan; Jun Wu 006; Zhifeng Zhang 001; Haoqi Ren (IEEE Trans. Multim., 2021)

Cache Placement Optimization in Mobile Edge Computing Networks With Unaware Environment - An Extended Multi-Armed Bandit Approach. - Yuqi Han; Lihua Ai; Rui Wang 001; Jun Wu 006; Dian Liu; Haoqi Ren (IEEE Trans. Wirel. Commun., 2021)

A Low-Cost Semihosting Approach to Debug DSP Application. - Tao Huang; Haoqi Ren; Zhifeng Zhang 001; Bin Tan; Jun Wu 006 (ChinaCom, 2022)

An Efficient Memory Management Method for Embedded Vector Processors. - Shengxuan Li; Haoqi Ren; Zhifeng Zhang 001; Bin Tan; Jun Wu 006 (ChinaCom, 2022)

Optimization of Tensor Operation in Compiler. - Chenguang Qiu; Jun Wu 006; Haoqi Ren; Zhifeng Zhang 001 (ChinaCom, 2022)

A Reconfigurable Convolutional Neural Networks Accelerator Based on FPGA. - Yalin Tang; Haoqi Ren; Zhifeng Zhang 001 (ChinaCom, 2022)

An Efficient DSP Simulator Design Supporting Multi-Core Debugging. - Wentao Qiao; Jun Wu 006; Haoqi Ren; Zhifeng Zhang 001; Bin Tan (ICCT, 2023)

An Efficient and Secure Inline Assembly Design for VLIW DSP. - Hao Yu; Jun Wu 006; Haoqi Ren; Zhifeng Zhang 001; Bin Tan (ICCT, 2023)