A 15.2-to-18.2GHz Balanced Dual-Core Inverse-Class-F VCO with Q-Enhanced 2nd-Harmonic Resonance Achieving 187-to-188.1dBc/Hz FoM in 28nm CMOS. - Xi Meng; Junqi Guo; Haoran Li 016; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (A-SSCC, 2021)

Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion. - Xi Meng; Haoran Li 016; Peng Chen 022; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

10.9 A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrms Jitter, -253.5dB FoMJ, and 0.55μs Locking Time Based on a Function-Reused VCO-Buffer and a Type-I FLL with Rapid Phase Alignment. - Haoran Li 016; Tailong Xu; Xi Meng; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (ISSCC, 2024)

A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment. - Haoran Li 016; Tailong Xu; Xi Meng; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

19.7 A 27GHz Fractional-N Sub-Sampling PLL Achieving 57.9fsrms Jitter, -249.7dB FoM, and 1.98µS Locking Time Using Polarity-Reversible SSPD. - Haoran Li 016; Jinge Li; Xueying Jiang; Xi Meng; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (ISSCC, 2025)

Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction. - Tailong Xu; Haoran Li 016; Xi Meng; Xiangxun Zhan; Yatao Peng; Jun Yin 001; Shiheng Yang; Chao Fan; Zhixiang Huang; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2025)