SHREC'22 track: Sketch-based 3D shape retrieval in the wild. - Jie Qin; Shuaihang Yuan; Jiaxin Chen; Boulbaba Ben Amor; Yi Fang 006; Nhat Hoang-Xuan; Chi-Bien Chu; Khoi-Nguyen Nguyen-Ngoc; Thien-Tri Cao; Nhat-Khang Ngô; Tuan-Luc Huynh; Hai-Dang Nguyen; et al. (Comput. Graph., 2022)

Cognitive multi-modal consistent hashing with flexible semantic transformation. - Junfeng An; Haoyang Luo; Zheng Zhang 006; Lei Zhu 002; Guangming Lu (Inf. Process. Manag., 2022)

A 65 nm 73 kb SRAM-Based Computing-In-Memory Macro With Dynamic-Sparsity Controlling. - Xin Qiao; Jiahao Song; Xiyuan Tang; Haoyang Luo; Nanbing Pan; Xiaoxin Cui; Runsheng Wang; Yuan Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 9.7fJ/Conv.-Step Capacitive Sensor Readout Circuit with Incremental Zoomed Time Domain Quantization. - Zilong Shen; Xiyuan Tang; Zhongyi Wu; Haoyang Luo; Zongnan Wang; Mingjie Liu; Xing Zhang 002; Yuan Wang 001 (CICC, 2023)

A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC. - Jiahao Song; Xiyuan Tang; Haoyang Luo; Haoyi Zhang; Xin Qiao; Zixuan Sun; Xiangxing Yang; Yuan Wang 001; Runsheng Wang; Ru Huang 001 (CICC, 2023)

SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility. - Haoyi Zhang; Xiaohan Gao; Haoyang Luo; Jiahao Song; Xiyuan Tang; Junhua Liu; Yibo Lin; Runsheng Wang; Ru Huang 001 (DATE, 2023)

Modality-Invariant Asymmetric Networks for Cross-Modal Hashing. - Zheng Zhang 006; Haoyang Luo; Lei Zhu 002; Guangming Lu; Heng Tao Shen (IEEE Trans. Knowl. Data Eng., 2023)

A 28nm 32Kb SRAM Computing-in-Memory Macro With Hierarchical Capacity Attenuator and Input Sparsity-Optimized ADC for 4b Mac Operation. - Kanglin Xiao; Xiaoxin Cui; Xin Qiao; Jiahao Song; Haoyang Luo; Xin'an Wang; Yuan Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 28nm 128TFLOPS/W Computing-In-Memory Engine Supporting One-Shot Floating-Point NN Inference and On-Device Fine-Tuning for Edge AI. - Haikang Diao; Haoyang Luo; Jiahao Song; Bocheng Xu; Runsheng Wang; Yuan Wang 001; Xiyuan Tang (CICC, 2024)

A 181.8dB FoMs Zoom Capacitance-to-Digital Converter with kT/C Noise Cancellation and Dead Band Operation. - Zilong Shen; Jiaiun Tang; Haoyang Luo; Zhongyi Wu; Zongnan Wang; Xing Zhang 002; Xiyuan Tang; Yuan Wang 001 (CICC, 2024)

30.5 A Variation-Tolerant In-eDRAM Continuous-Time Ising Machine Featuring 15-Level Coefficients and Leaked Negative-Feedback Annealing. - Jiahao Song; Zihan Wu 005; Xiyuan Tang; Bocheng Xu; Haoyang Luo; Youming Yang 002; Yuan Wang 001; Runsheng Wang; Ru Huang 001 (ISSCC, 2024)

Exploiting Descriptive Completeness Prior for Cross Modal Hashing with Incomplete Labels. - Haoyang Luo; Zheng Zhang 006; Yadan Luo (NeurIPS, 2024)

A 4-bit Calibration-Free Computing-In-Memory Macro With 3T1C Current-Programed Dynamic-Cascode Multi-Level-Cell eDRAM. - Jiahao Song; Xiyuan Tang; Haoyang Luo; Haoyi Zhang; Xin Qiao; Zixuan Sun; Xiangxing Yang; Zihan Wu 005; Yuan Wang 001; Runsheng Wang; Ru Huang 001 (IEEE J. Solid State Circuits, 2024)

A 28nm 8Kb Reconfigurable SRAM Computing-In-Memory Macro With Input-Sparsity Optimized DTC for Multi-Mode MAC Operations. - Kanglin Xiao; Xin Qiao; Xiaoxin Cui; Jiahao Song; Haoyang Luo; Xin'an Wang; Yuan Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

CASCADE: A Framework for CNN Accelerator Synthesis With Concatenation and Refreshing Dataflow. - Qingyu Guo; Haoyang Luo; Meng Li 004; Xiyuan Tang; Yuan Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Contrastive Incomplete Cross-Modal Hashing. - Haoyang Luo; Zheng Zhang 006; Liqiang Nie (IEEE Trans. Knowl. Data Eng., 2024)

A 266F2 Ultra Stable Differential NOR-Structured Physically Unclonable Function With < 6x10-9 Bit Error Rate Through Efficient Redundancy Strategy. - Haoyi Zhang; Jiahao Song; Haoyang Luo; Xiyuan Tang; Yuan Wang 001; Runsheng Wang; Ru Huang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 4.82-µW 183.4dB-FoMSNDR CT Incremental Tracking-Zoom Sensor Readout Frontend with Floating-Gm-CCO Integrator. - Haoyang Luo; Zongnan Wang; Jiarui Wang; Bingrui Li; Zilong Shen; Yang Liu; Xiaojie Duan; Yuan Wang 001; Xiyuan Tang (CICC, 2025)

SeqAfford: Sequential 3D Affordance Reasoning via Multimodal Large Language Model. - Chunlin Yu; Hanqing Wang 007; Ye Shi 001; Haoyang Luo; Sibei Yang; Jingyi Yu; Jingya Wang (CVPR, 2025)

SEGA-DCIM: Design Space Exploration-Guided Automatic Digital CIM Compiler with Multiple Precision Support. - Haikang Diao; Haoyi Zhang; Jiahao Song; Haoyang Luo; Yibo Lin; Runsheng Wang; Yuan Wang 001; Xiyuan Tang (DATE, 2025)

A 185.2dB-FoMs 8.7aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique. - Bingrui Li; Zilong Shen; Haoyang Luo; Jiachang Yang; Zongnan Wang; Yuan Wang 001; Xiyuan Tang (ISSCC, 2025)

A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation Technique. - Zongnan Wang; Bingrui Li; Jiajun Tang; Zhongyi Wu; Haoyang Luo; Yuan Wang 001; Xiyuan Tang (ISSCC, 2025)

37.5 SKADI: A 28nm Complete K-SAT Solver Featuring Dual-Path SRAM-Based Macro and Incremental Update with 100% Solvability. - Zihan Wu 005; Xiyuan Tang; Tao Zhang; Lishan Lin; Haoyang Luo; Bocheng Xu; Zhongyi Wu; Jiahao Song; Yitao Liang; Xiaochen Bo; Yuan Wang 001 (ISSCC, 2025)

A Multiply-Less Approximate SRAM Compute-In-Memory Macro for Neural-Network Inference. - Haikang Diao; Yifan He 003; Xuan Li; Chen Tang; Wenbin Jia; Jinshan Yue; Haoyang Luo; Jiahao Song; Xueqing Li 002; Huazhong Yang; Hongyang Jia; Yongpan Liu; et al. (IEEE J. Solid State Circuits, 2025)

Beyond One-Hot Labels: Semantic Mixing for Model Calibration. - Haoyang Luo; Linwei Tao; Minjing Dong; Chang Xu (CoRR, 2025)

GenPO: Generative Diffusion Models Meet On-Policy Reinforcement Learning. - Shutong Ding; Ke Hu; Shan Zhong; Haoyang Luo; Weinan Zhang 001; Jingya Wang; Jun Wang; Ye Shi 001 (CoRR, 2025)

A Variation-Tolerant Continuous-Time Ising Machine With eDRAM-Based Spin Interaction and Leaked Negative Feedback Annealing. - Zihan Wu 005; Jiahao Song; Xiyuan Tang; Bocheng Xu; Haoyang Luo; Youming Yang 002; Runsheng Wang; Xiaochen Bo; Yuan Wang 001 (IEEE J. Solid State Circuits, 2025)

Sample Margin-Aware Recalibration of Temperature Scaling. - Haolan Guo; Linwei Tao; Haoyang Luo; Minjing Dong; Chang Xu 002 (CoRR, 2025)