OCEAN: An on-chip incremental-learning enhanced processor with gated recurrent neural network accelerators. - Chixiao Chen; Hongwei Ding; Huwan Peng; Haozhe Zhu; Rui Ma; Peiyong Zhang; Xiaolang Yan; Yu Wang 046; Mingyu Wang 001; Hao Min; Chuanjin Richard Shi (ESSCIRC, 2017)

OCEAN: An On-Chip Incremental-Learning Enhanced Artificial Neural Network Processor With Multiple Gated-Recurrent-Unit Accelerators. - Chixiao Chen; Hongwei Ding; Huwan Peng; Haozhe Zhu; Yu Wang 046; Chuanjin Richard Shi (IEEE J. Emerg. Sel. Topics Circuits Syst., 2018)

TRPN: Matrix Factorization Meets Recurrent Neural Network for Temporal Rating Prediction. - Haozhe Zhu; Yanyan Shen; Xian Zhou 003 (APWeb/WAIM (2), 2019)

XNORAM: An Efficient Computing-in-Memory Architecture for Binary Convolutional Neural Networks with Flexible Dataflow Mapping. - Shiwei Liu 002; Haozhe Zhu; Chixiao Chen; Lihua Zhang; Chuanjin Richard Shi (AICAS, 2020)

Tanji: a General-purpose Neural Network Accelerator with Unified Crossbar Architecture. - Haozhe Zhu; Yu Wang 046; Chuanjin Richard Shi (IEEE Des. Test, 2020)

A Communication-Aware DNN Accelerator on ImageNet Using In-Memory Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in 65-nm CMOS. - Haozhe Zhu; Chixiao Chen; Shiwei Liu 002; Qiaosha Zou; Mingyu Wang 001; Lihua Zhang; Xiaoyang Zeng; Chuanjin Richard Shi (IEEE J. Emerg. Sel. Topics Circuits Syst., 2020)

An Efficient Markov Random Field Based Denoising Approach for Dynamic Vision Sensor. - Xi Cheng; Haozhe Zhu; Jingjing Liu 004; Mingyu Wang 001; Xiaoyang Zeng (ASICON, 2021)

A 0.57-GOPS/DSP Object Detection PIM Accelerator on FPGA. - Bo Jiao; Jinshan Zhang 006; Yuanyuan Xie; Shunli Wang 001; Haozhe Zhu; Xiaoyang Kang 001; Zhiyan Dong; Lihua Zhang; Chixiao Chen (ASP-DAC, 2021)

Computing Utilization Enhancement for Chiplet-based Homogeneous Processing-in-Memory Deep Learning Processors. - Bo Jiao; Haozhe Zhu; Jinshan Zhang 006; Shunli Wang 001; Xiaoyang Kang 001; Lihua Zhang; Mingyu Wang 001; Chixiao Chen (ACM Great Lakes Symposium on VLSI, 2021)

ALPINE: An Agile Processing-in-Memory Macro Compilation Framework. - Jinshan Zhang 006; Bo Jiao; Yunzhengmao Wang; Haozhe Zhu; Lihua Zhang; Chixiao Chen (ACM Great Lakes Symposium on VLSI, 2021)

A 11.6μ W Computing-on-Memory-Boundary Keyword Spotting Processor with Joint MFCC-CNN Ternary Quantization. - Xinru Jia; Haozhe Zhu; Yunzheng Wang; Jinshan Zhang 006; Feng Lin; Xiankui Xiong; Dong Xu 015; Chixiao Chen; Qi Liu 010 (ISCAS, 2022)

COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning. - Haozhe Zhu; Bo Jiao; Jinshan Zhang 006; Xinru Jia; Yunzhengmao Wang; Tianchan Guan; Shengcheng Wang; Dimin Niu; Hongzhong Zheng; Chixiao Chen; Mingyu Wang 001; Lihua Zhang; et al. (ISSCC, 2022)

Road Defect Detection Based on Semantic Transformed Disparity Image Segmentation. - Li Wang; Wenbo Shi; Haozhe Zhu; Denghuang Zhang; Yikang Zhang; Jiahe Fan; Mohammud Junaid Bocus (ROBIO, 2022)

A 28 nm 81 Kb 59-95.3 TOPS/W 4T2R ReRAM Computing-in-Memory Accelerator With Voltage-to-Time-to-Digital Based Output. - Keji Zhou; Xinru Jia; Chenyang Zhao 008; Xumeng Zhang; Guangjian Wu; Chen Mu; Haozhe Zhu; Yanting Ding; Chixiao Chen; Xiaoyong Xue; Xiaoyang Zeng; Qi Liu 010 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

Bit-Offsetter: A Bit-serial DNN Accelerator with Weight-offset MAC for Bit-wise Sparsity Exploitation. - Siqi He; Hongyi Zhang; Mengjie Li; Haozhe Zhu; Chixiao Chen; Qi Liu 010; Xiaoyang Zeng (AICAS, 2023)

A $2.53 mu mathrm{W}/ text{channel}$ Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros. - Hao Jiang 024; Jiapei Zheng; Yunzhengmao Wang; Jinshan Zhang 006; Haozhe Zhu; Liangjian Lyu; Yingping Chen; Chixiao Chen; Qi Liu 010 (ISCAS, 2023)

A Scalable Die-to-Die Interconnect with Replay and Repair Schemes for 2.5D/3D Integration. - Jie Liao; Bo Jiao; Jinshan Zhang 006; Shiwei Liu 002; Hao Jiang 024; Jun Tao 001; Wenning Jiang; Qi Liu 010; Lihua Zhang; Haozhe Zhu; Chixiao Chen (ISCAS, 2023)

A 28nm 53.8TOPS/W 8b Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper for Unstructured-Pruned NN and CIM-Based Local-Attention-Reusable Engine. - Shiwei Liu 002; Peizhe Li; Jinshan Zhang 006; Yunzhengmao Wang; Haozhe Zhu; Wenning Jiang; Shan Tang; Chixiao Chen; Qi Liu 010; Ming Liu 022 (ISSCC, 2023)

A Real-Time Optical-Flow-based SLAM FPGA Accelerator with Inter-Frame Similarity Exploitation and Correlation-Guided Mixed-Precision Flow Update. - Mengjie Li; Haozhe Zhu; Yiming Zhang; Siqi He; Qi Liu 010; Xiaoyang Zeng; Chixiao Chen (A-SSCC, 2024)

A 28nm 76.25TOPS/W RRAM/SRAM-Collaborative CIM Fine-Tuning Accelerator with RRAM-Endurance/Latency-Aware Weight Allocation for CNN and Transformer. - Chen Mu; Zhirui Huang; Hao Jiang 024; Jie Liao; Bo Jiao; Yuliang Zhou; Haozhe Zhu; Jianguo Yang; Qi Liu 010; Chixiao Chen (A-SSCC, 2024)

ST-BPTT: A Memory-efficient BPTT SNN Training Approach through Gradient-Contribution-Driven Time-Step Selection. - Jiajun Lu; Haozhe Zhu; Xiaoyang Zeng; Chixiao Chen (BioCAS, 2024)

ARCTIC: Agile and Robust Compute-In-Memory Compiler with Parameterized INT/FP Precision and Built-In Self Test. - Hongyi Zhang; Haozhe Zhu; Siqi He; Mengjie Li; Chengchen Wang; Xiankui Xiong; Haidong Tian; Xiaoyang Zeng; Chixiao Chen (DATE, 2024)

A 19.7 TFLOPS/W Multiply-less Logarithmic Floating-Point CIM Architecture with Error-Reduced Compensated Approximate Adder. - Mengjie Li; Hongyi Zhang; Siqi He; Haozhe Zhu; Hao Zhang; Jinglei Liu; Jiayuan Chen; Zhenping Hu; Xiaoyang Zeng; Chixiao Chen (ISCAS, 2024)

GauSPU: 3D Gaussian Splatting Processor for Real-Time SLAM Systems. - Lizhou Wu; Haozhe Zhu; Siqi He; Jiapei Zheng; Chixiao Chen; Xiaoyang Zeng (MICRO, 2024)

FAM-Former: Global Transformer and Feature Aggregation Module for Knee MRI Age Estimation. - Linchao He; Haozhe Zhu; Xiaodong Deng; Fei Fan; Peixi Liao; Wenchao Du; Hu Chen 002; Zhenhua Deng; Yi Zhang 018 (IEEE Trans. Instrum. Meas., 2024)

Trident-CIM: A LUT-Based Compute-in-Memory Macro With Trident Read Bit-Line and Partial Product Pruning. - Haozhe Zhu; Hongyi Zhang; Siqi He; Mengjie Li; Xiaoyang Zeng; Chixiao Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

FPIA: Communication-Aware Multi-Chiplet Integration With Field-Programmable Interconnect Fabric on Reusable Silicon Interposer. - Bo Jiao; Lei Xu; Xinyu Yu; Haitao Yang; Haozhe Zhu; Yu Wang; Jundong Zhu; Dexin Wen; Lingli Wang; Jun Tao 001; Chixiao Chen; Yinhe Han 001; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

SLAM-CIM: A Visual SLAM Backend Processor With Dynamic-Range-Driven-Skipping Linear-Solving FP-CIM Macros. - Mengjie Li; Haozhe Zhu; Siqi He; Hongyi Zhang; Jie Liao; Danfeng Zhai; Chixiao Chen; Qi Liu 010; Xiaoyang Zeng; Ninghui Sun; Ming Liu 022 (IEEE J. Solid State Circuits, 2024)

Hi-NeRF: A Multicore NeRF Accelerator With Hierarchical Empty Space Skipping for Edge 3-D Rendering. - Lizhou Wu; Haozhe Zhu; Jiapei Zheng; Mengjie Li; Yinuo Cheng; Qi Liu 010; Xiaoyang Zeng; Chixiao Chen (IEEE Trans. Very Large Scale Integr. Syst., 2024)

EIGEN: Enabling Efficient 3DIC Interconnect with Heterogeneous Dual-Layer Network-on-Active-Interposer. - Siyao Jia; Bo Jiao; Haozhe Zhu; Chixiao Chen; Qi Liu 010; Ming Liu 022 (HPCA, 2025)

A 0.22 pJ/bit Processing-in-Controller GEMV Macro with Weight Prefetch for Efficient Near-Memory Computing. - Jie Yang; Jiapei Zheng; Siqi He; Lizhou Wu; Chen Mu; Haozhe Zhu; Liyu Lin; Qi Liu 010; Chixiao Chen (ISCAS, 2025)

37.4 SHINSAI: A 586mm2 Reusable Active TSV Interposer with Programmable Interconnect Fabric and 512Mb 3D Underdeck Memory. - Bo Jiao; Haozhe Zhu; Yuman Zeng; Yongjiang Li; Jie Liao; Siyao Jia; Mochen Tian; Zexing Chen; Jundong Zhu; Dexin Wen; Yan Wang; Yu Wang 046; et al. (ISSCC, 2025)

Federated-Continual Dynamic Segmentation of Histopathology Guided by Barlow Continuity. - Niklas Babendererde; Haozhe Zhu; Moritz Fuchs; Jonathan Stieber; Anirban Mukhopadhyay 003 (WACV, 2025)

An optimization architecture for multi-timescale energy scheduling under renewable uncertainty. - Qingcheng Lin; Haozhe Zhu; Xuefeng Li; Hui Xiao (Comput. Ind. Eng., 2025)

SSDM: Generated image interaction method based on spatial sparsity for diffusion models. - Zhuochao Yang; Jingjing Liu 004; Haozhe Zhu; Jianhua Zhang; Wanquan Liu (Neurocomputing, 2025)

FIT-Print: Towards False-claim-resistant Model Ownership Verification via Targeted Fingerprint. - Shuo Shao 002; Haozhe Zhu; Hongwei Yao; Yiming Li 004; Tianwei Zhang 004; Zhan Qin; Kui Ren 001 (CoRR, 2025)