Hardware implementation of an EAN-13 bar code decoder. - Jeroen De Maeyer; Harald Devos; Wim Meeus; Peter Verplaetse; Dirk Stroobandt (ASP-DAC, 2003)

Reconfigurable Hardware for a Scalable Wavelet Video Decoder and Its Performance Requirements. - Dirk Stroobandt; Hendrik Eeckhaut; Harald Devos; Mark Christiaens; Fabio Verdicchio; Peter Schelkens (SAMOS, 2004)

A Hardware-Friendly Wavelet Entropy Codec for Scalable Video. - Hendrik Eeckhaut; Harald Devos; Benjamin Schrauwen; Mark Christiaens; Dirk Stroobandt (DATE, 2005)

07041 Working Group - Towards Interfaces for Integrated Performance and Power Analysis and Simulation. - Chris J. Bleakley; Tom Clerckx; Harald Devos; Matthias Grumer; Alex Janek; Ulrich Kremer; Christian W. Probst; Phillip Stanley-Marbell; Christian Steger; Vasanth Venkatachalam; Manuel Wendt (Power-aware Computing Systems, 2007)

Energy Scalability and the RESUME Scalable Video Codec. - Harald Devos; Hendrik Eeckhaut; Mark Christiaens; Dirk Stroobandt (Power-aware Computing Systems, 2007)

The Energy Scalability of Wavelet-Based, Scalable Video Decoding. - Hendrik Eeckhaut; Harald Devos; Dirk Stroobandt (PATMOS, 2007)

FPGA Design Methodology for a Wavelet-Based Scalable Video Decoder. - Hendrik Eeckhaut; Harald Devos; Philippe Faes; Mark Christiaens; Dirk Stroobandt (SAMOS, 2007)

Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations. - Harald Devos; Kristof Beyls; Mark Christiaens; Jan M. Van Campenhout; Erik H. D'Hollander; Dirk Stroobandt (Trans. High Perform. Embed. Archit. Compil., 2007)

Scalable, Wavelet-Based Video: From Server to Hardware-Accelerated Client. - Hendrik Eeckhaut; Harald Devos; Peter Lambert; Davy De Schrijver; Wim Van Lancker; Vincent Nollet; Prabhat Avasare; Tom Clerckx; Fabio Verdicchio; Mark Christiaens; Peter Schelkens; Rik Van de Walle; et al. (IEEE Trans. Multim., 2007)

Embedding Smart Buffers for Window Operations in a Stream-Oriented C-to-VHDL Compiler. - Fabian Diet; Erik H. D'Hollander; Kristof Beyls; Harald Devos (DELTA, 2008)

Loop Transformations to Reduce the Dynamic FPGA Recon?guration Overhead. - Tom Degryse; Karel Bruneel; Harald Devos; Dirk Stroobandt (ReConFig, 2008)

Loop Transformations for the Optimized Generation of Reconfigurable Hardware. - Harald Devos (2008)

Optimizing the FPGA Memory Design for a Sobel Edge Detector. - Craig Moore; Harald Devos; Dirk Stroobandt (ERSA, 2009)

Applying Parameterizable Dynamic Configurations to Sequence Alignment. - Tom Davidson; Karel Bruneel; Harald Devos; Dirk Stroobandt (PARCO, 2009)

Towards a Tighter Integration of Generated and Custom-Made Hardware. - Harald Devos; Wim Meeus; Dirk Stroobandt (ARC, 2010)

A Parallel for Loop Memory Template for a High Level Synthesis Compiler. - Craig Moore; Wim Meeus; Harald Devos; Dirk Stroobandt (DSD, 2010)

Automatic tool flow for shift-register-LUT reconfiguration: making run-time reconfiguration fast and easy (abstract only). - Brahim Al Farisi; Karel Bruneel; Harald Devos; Dirk Stroobandt (FPGA, 2010)

Constructing Application-Specific Memory Hierarchies on FPGAs. - Harald Devos; Jan Van Campenhout; Ingrid Verbauwhede; Dirk Stroobandt (Trans. High Perform. Embed. Archit. Compil., 2011)