Der Instrumentenrechner der Halley Multicolour Camera. - E. Krahn; Fritz Gliem; Harald Michalik; Peter Rüffer (ARCS, 1986)

Image data compressor for Huygens' DISR instrument compared to state of the art compression schemes. - Peter Rueffer; Harald Michalik; Fritz Gliem; Frank Rabe (IGARSS, 2004)

Enhancements of reconfigurable System-on-Chip Data Processing Units for Space Application. - Björn Osterloh; Harald Michalik; Björn Fiethe; Frank Bubenhagen (AHS, 2007)

Reconfigurable system-on-chip data processing units for space imaging instruments. - Björn Fiethe; Harald Michalik; C. Dierker; Björn Osterloh; Gang Zhou (DATE, 2007)

Efficient and High-Throughput Implementations of AES-GCM on FPGAs. - Gang Zhou; Harald Michalik; László Hinsenkamp (FPT, 2007)

SoCWire: A Network-on-Chip Approach for Reconfigurable System-on-Chip Designs in Space Applications. - Björn Osterloh; Harald Michalik; Björn Fiethe; Karel Kotarowski (AHS, 2008)

Networked Architecture for Distributed PC-based Robot Control Systems. - Yannick Dadji; Jochen Maaß; Harald Michalik; Tobias Möglich; Nnamdi Kohn; J. Uwe Varchmin (ARCS, 2008)

Area optimization of bit parallel finite field multipliers with fast carry logic on FPGAS. - Gang Zhou; Li Li 027; Harald Michalik (FPL, 2008)

Dynamic Partial Reconfiguration in Space Applications. - Björn Osterloh; Harald Michalik; Sandi Habinc; Björn Fiethe (AHS, 2009)

Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs. - Gang Zhou; Harald Michalik; László Hinsenkamp (ARC, 2009)

SoCWire: A Robust and Fault Tolerant Network-on-Chip Approach for a Dynamic Reconfigurable System-on-Chip in FPGAs. - Björn Osterloh; Harald Michalik; Björn Fiethe (ARCS, 2009)

Parallel Architecture For Real Time Control System Based On The IEEE1394 Standard. - Yannick Dadji Foyet; Harald Michalik; Tobias Möglich (PDPTA, 2009)

Architecture verification of the SoCWire NoC approach for safe dynamic partial reconfiguration in space applications. - Björn Osterloh; Harald Michalik; Björn Fiethe; Frank Bubenhagen (AHS, 2010)

Comments on "A New Architecture for a Parallel Finite Field Multiplier with Low Complexity Based on Composite Field". - Gang Zhou; Harald Michalik (IEEE Trans. Computers, 2010)

Complexity Analysis and Efficient Implementations of Bit Parallel Finite Field Multipliers Based on Karatsuba-Ofman Algorithm on FPGAs. - Gang Zhou; Harald Michalik; László Hinsenkamp (IEEE Trans. Very Large Scale Integr. Syst., 2010)

AMBA to SoCWire network on Chip bridge as a backbone for a Dynamic Reconfigurable Processing unit. - Holger Michel; Frank Bubenhagen; Björn Fiethe; Harald Michalik; Björn Osterloh; Wayne Sullivan; Alex Wishart; Jørgen Ilstad; Sandi Habinc (AHS, 2011)

A Communication Architecture for Distributed Real-Time Robot Control. - Yannick Dadji; Harald Michalik; Nnamdi Kohn; Jens Steiner; Guido Beckmann; Tobias Möglich; J. Uwe Varchmin (Robotic Systems for Handling and Assembly, 2011)

Adaptive hardware by dynamic reconfiguration for the Solar Orbiter PHI instrument. - Björn Fiethe; Frank Bubenhagen; Tobias Lange 002; Harald Michalik; Holger Michel; Joachim Woch; Johann Hirzberger (AHS, 2012)

The SoCWire protocol (SoCP): A flexible and minimal protocol for a Network-on-Chip. - Holger Michel; Adrian Belger; Frank Bubenhagen; Björn Fiethe; Harald Michalik; Wayne Sullivan; Alex Wishart; Jørgen Ilstad (AHS, 2012)

Complexity Analysis of Finite Field Digit Serial Multipliers on FPGAs. - Gang Zhou; Li Li 027; Harald Michalik (ARC, 2012)

Institut für Datentechnik und Kommunikationsnetze - Mitgestaltung der Informatik in Braunschweig. - Rolf Ernst; Harald Michalik; Peter Rüffer (40 Jahre Informatik @ Braunschweig, 2012)

Reconfigurable platforms for Data Processing on scientific space instruments. - Frank Bubenhagen; Björn Fiethe; Tobias Lange 002; Harald Michalik; Holger Michel (AHS, 2013)

Worst case error rate predictions and mitigation schemes for Virtex-4 FPGAs on solar orbiter. - Holger Michel; Frank Bubenhagen; Kai Grurmann; Tobias Lange 002; Björn Fiethe; Harald Michalik (AHS, 2013)

Efficient reconfiguration of processing modules on FPGAs for space instruments. - Sándor P. Fekete; Björn Fiethe; Stephan Friedrichs; Harald Michalik; Christos Orlis (AHS, 2014)

Dependable reconfigurable space systems: Challenges, new trends and case studies. - Antonis M. Paschalis; Harald Michalik; Nektarios Kranitis; Celia López-Ongil; Pedro Reviriego Vasallo (IOLTS, 2014)

Read back scrubbing for SRAM FPGAs in a data processing unit for space instruments. - Holger Michel; Adrian Belger; Tobias Lange 002; Björn Fiethe; Harald Michalik (AHS, 2015)

Resource-efficient dynamic partial reconfiguration on FPGAs for space instruments. - Alexander Dörflinger; Björn Fiethe; Harald Michalik; Sándor P. Fekete; Phillip Keldenich; Christian Scheffer (AHS, 2017)

On-board processing using reconfigurable hardware on the solar orbiter PHI instrument. - Tobias Lange 002; Björn Fiethe; Holger Michel; Harald Michalik; Kinga Albert; Johann Hirzberger (AHS, 2017)

SEU fault classification by fault injection for an FPGA in the space instrument SOPHI. - Holger Michel; Hipólito Guzmán-Miranda; Alexander Dörflinger; Harald Michalik; Miguel Aguirre Aguirre Echánove (AHS, 2017)

Hardware and Software Task Scheduling for ARM-FPGA Platforms. - Alexander Dörflinger; Mark Albers; Johannes Schlatow; Björn Fiethe; Harald Michalik; Phillip Keldenich; Sándor P. Fekete (AHS, 2018)

Hardware Acceleration in Genode OS Using Dynamic Partial Reconfiguration. - Alexander Dörflinger; Mark Albers; Björn Fiethe; Harald Michalik (ARCS, 2018)

Electronic Automotive and Aerospace Systems - a Master Programme on electronics design for safety critical applications. - Harald Michalik; Holger Dinse (EWME, 2018)

Demonstrating Controlled Change for Autonomous Space Vehicles. - Alexander Dörflinger; Mark Albers; Björn Fiethe; Harald Michalik; Mischa Möstl; Johannes Schlatow; Rolf Ernst (AHS, 2019)

Self-Adaptation for Availability in CPU-FPGA Systems Under Soft Errors. - Mischa Möstl; Alexander Dörflinger; Mark Albers; Harald Michalik; Rolf Ernst (AHS, 2019)

ECC Memory for Fault Tolerant RISC-V Processors. - Alexander Dörflinger; Yejun Guan; Sören Michalik; Sönke Michalik; Jamin Naghmouchi; Harald Michalik (ARCS, 2020)

A comparative survey of open-source application-class RISC-V processor implementations. - Alexander Dörflinger; Mark Albers; Benedikt Kleinbeck; Yejun Guan; Harald Michalik; Raphael Klink; Christopher Blochwitz; Anouar Nechi; Mladen Berekovic (CF, 2021)

A Framework for Fault Tolerance in RISC-V. - Alexander Dörflinger; Benedikt Kleinbeck; Mark Albers; Harald Michalik; Martin Moya (DASC/PiCom/CBDCom/CyberSciTech, 2022)