A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS. - Woo-Rham Bae; Haram Ju; Kwanseo Park; Sung-Yong Cho; Deog-Kyoon Jeong (A-SSCC, 2015)

A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm. - Gyu-Seob Jeong; Sang-Hyeok Chu; Yoonsoo Kim; Sungchun Jang; Sungwoo Kim 001; Woo-Rham Bae; Sung-Yong Cho; Haram Ju; Deog-Kyoon Jeong (A-SSCC, 2015)

A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS. - Kwanseo Park; Woo-Rham Bae; Haram Ju; Jinhyung Lee; Gyu-Seob Jeong; Yoonsoo Kim; Deog-Kyoon Jeong (ISCAS, 2015)

A 6-to-32 Gb/s voltage-mode transmitter with scalable supply, voltage swing, and pre-emphasis in 65-nm CMOS. - Woo-Rham Bae; Haram Ju; Kwanseo Park; Deog-Kyoon Jeong (A-SSCC, 2016)

A 800-Mb/s 0.89-pJ/b reference-less optical receiver with pulse-position-modulation scheme. - Haram Ju; Woo-Rham Bae; Gyu-Seob Jeong; Deog-Kyoon Jeong (ISCAS, 2016)

A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS. - Woo-Rham Bae; Haram Ju; Kwanseo Park; Sung-Yong Cho; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2016)

A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- Gm Bias. - Gyu-Seob Jeong; Sang-Hyeok Chu; Yoonsoo Kim; Sungchun Jang; Sungwoo Kim 001; Woo-Rham Bae; Sung-Yong Cho; Haram Ju; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2016)

A 28 Gb/s 1.6 pJ/b PAM-4 Transmitter Using Fractionally Spaced 3-Tap FFE and Gm-Regulated Resistive-Feedback Driver. - Haram Ju; Moon-Chul Choi; Gyu-Seob Jeong; Woo-Rham Bae; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A 64 GB/s 1.5 PJ/Bit PAM-4 Transmitter with 3-Tap FFE and GM-Regulated Active-Feedback Driver in 28 NM CMOS. - Haram Ju; Moon-Chul Choi; Gyu-Seob Jeong; Deog-Kyoon Jeong (VLSI Circuits, 2018)

A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards. - Woo-Rham Bae; Haram Ju; Kwanseo Park; Jaeduk Han; Deog-Kyoon Jeong (IEEE Trans. Ind. Electron., 2018)

A Design of Data Path Based on CMOS Logic for a 72-Gb/s PAM-4 Transmitter in 28-nm CMOS. - Moon-Chul Choi; Haram Ju; Han-Gon Ko; Deog-Kyoon Jeong (ICEIC, 2019)

A 2.5-28 Gb/s Multi-Standard Transmitter With Two-Step Time-Multiplexing Driver. - Moon-Chul Choi; Deog-Kyoon Jeong; Sung-Yong Cho; Minkyo Shim; Byungmin Kim; Han-Gon Ko; Haram Ju; Kwanseo Park; Hyojun Kim; Kwandong Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Modulo-FIR Equalizer for Wireline Communications. - Gyu-Seob Jeong; Byungjun Kang; Haram Ju; Kwanseo Park; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Maximum-Eye-Tracking CDR With Biased Data-Level and Eye Slope Detector for Near-Optimal Timing Adaptation. - Hye-Yoon Joo; Jinhyung Lee; Haram Ju; Han-Gon Ko; Jungmin Yoon; Byungjun Kang; Deog-Kyoon Jeong (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A 48Gb/s 2.4pJ/b PAM-4 Baud-Rate Digital CDR with Stochastic Phase Detection Technique in 40nm CMOS. - Haram Ju; Kwangho Lee; Woosong Jung; Deog-Kyoon Jeong (A-SSCC, 2021)

A 48 Gb/s PAM4 receiver with Baud-rate phase-detector for multi-level signal modulation in 40 nm CMOS. - Kwangho Lee; Woosong Jung; Haram Ju; Jinhyung Lee; Deog-Kyoon Jeong (A-SSCC, 2021)

An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS. - Kwangho Lee; Hyojun Kim; Woosong Jung; Jinhyung Lee; Haram Ju; Kwanseo Park; Ook Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector. - Haram Ju; Kwangho Lee; Kwanseo Park; Woosong Jung; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2022)

A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS. - Woosong Jung; Kwangho Lee; Kwanseo Park; Haram Ju; Jinhyung Lee; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2023)