Enabling Concurrent Clock and Power Gating in 32 Bit ROM. - Harekrishna Kumar; Anjan Kumar; Vinay Kumar Deolia (ICCCNT, 2018)

Design of Low Power with Expanded Noise Margin Subthreshold 12T SRAM Cell for Ultra-Low Power Devices. - Harekrishna Kumar; V. K. Tomar (J. Circuits Syst. Comput., 2021)

A Review on Performance Evaluation of Different Low Power SRAM Cells in Nano-Scale Era. - Harekrishna Kumar; V. K. Tomar (Wirel. Pers. Commun., 2021)

Design of Low Leakage 9T SRAM Cell with Improved Performance for Ultra-Low Power Devices. - Harekrishna Kumar; V. K. Tomar (J. Circuits Syst. Comput., 2022)

Epidemiological Mucormycosis treatment and diagnosis challenges using the adaptive properties of computer vision techniques based approach: a review. - Nira; Harekrishna Kumar (Multim. Tools Appl., 2022)