Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS. - Hari Ananthan; Chris H. Kim; Kaushik Roy 001 (ISLPED, 2004)

FinFET SRAM - Device and Circuit Design Considerations. - Hari Ananthan; Aditya Bansal; Kaushik Roy 001 (ISQED, 2004)

A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS. - Hari Ananthan; Kaushik Roy 001 (DAC, 2006)

Double-Gate SOI Devices for Low-Power and High-Performance Applications. - Kaushik Roy 001; Hamid Mahmoodi-Meimand; Saibal Mukhopadhyay; Hari Ananthan; Aditya Bansal; Tamer Cakici (VLSI Design, 2006)