Testable Design of Reversible Circuits Using Parity Preserving Gates. - Hari Mohan Gaur; Ashutosh Kumar Singh 001; Umesh Ghanekar (IEEE Des. Test, 2018)

Offline Testing of Reversible Logic Circuits: An Analysis. - Hari Mohan Gaur; Ashutosh Kumar Singh 001; Umesh Ghanekar (Integr., 2018)

Design of Reversible Arithmetic Logic Unit with Built-In Testability. - Hari Mohan Gaur; Ashutosh Kumar Singh 001; Umesh Ghanekar (IEEE Des. Test, 2019)

Fault detection in multiple controlled Fredkin circuits. - Ashutosh Kumar Singh 001; Hari Mohan Gaur; Umesh Ghanekar (IET Circuits Devices Syst., 2019)

Testable Designs of Toffoli Fredkin Reversible Circuits. - Hari Mohan Gaur; Ashutosh Kumar Singh 001; Umesh Ghanekar (CoRR, 2021)

Design of Single-Bit Fault-Tolerant Reversible Circuits. - Hari Mohan Gaur; Ashutosh Kumar Singh 001; Anand Mohan; Masahiro Fujita; Dhiraj K. Pradhan (IEEE Des. Test, 2021)

An Efficient Design of Scalable Reversible Multiplier with Testability. - Hari Mohan Gaur; Ashutosh Kumar Singh 001; Umesh Ghanekar (J. Circuits Syst. Comput., 2022)

Comprehensive and Comparative Analysis of QCA-based Circuit Designs for Next-generation Computation. - Vaibhav Jain; Devendra Kumar Sharma; Hari Mohan Gaur; Ashutosh Kumar Singh 001; Xiaoqing Wen (ACM Comput. Surv., 2024)