An Area Efficient Mixed-Signal Test Architecture for Systems-on-a-Chip. - Hari Vijay Venkatanarayanan; Michael L. Bushnell (VLSI Design, 2006)

A Neural Net Branch Predictor to Reduce Power. - Rajamani Sethuram; Omar I. Khan; Hari Vijay Venkatanarayanan; Michael L. Bushnell (VLSI Design, 2007)

A Jitter Reduction Circuit Using Autocorrelation for Phase-Locked Loops and Serializer-Deserializer (SERDES) Circuits. - Hari Vijay Venkatanarayanan; Michael L. Bushnell (VLSI Design, 2008)

TOGGLE6.0: A 4.8Gbps Next Generation Area and Power Efficient Transceiver for Flash Memory Interface. - Hari Vijay Venkatanarayanan; Rustum Prasad Sahu; Maheswara Alamuru; Ergam Reddy Battini; Syed Mohammed Haroon; Saurav Suman; Deepika Mallela; Sanjeeb Kumar Ghosh; Billy Koo (VLSID, 2025)