AttriNet: learning mid-level features for human activity recognition with deep belief networks. - Harideep Nair; Cathy Tan; Ming Zeng 009; Ole J. Mengshoel; John Paul Shen (UbiComp/ISWC Adjunct, 2019)

Freeflow Core: Enhancing Performance of In-Order Cores with Energy Efficiency. - Raj Kumar Choudhary; Newton Singh; Harideep Nair; Rishabh Rawat; Virendra Singh (ICCD, 2019)

Hardware Aware Neural Network Architectures using FbNet. - Sai Vineeth Kalluru Srinivas; Harideep Nair; Vinay Vidyasagar (CoRR, 2019)

Direct CMOS Implementation of Neuromorphic Temporal Neural Networks for Sensory Processing. - Harideep Nair; John Paul Shen; James E. Smith 001 (CoRR, 2020)

Unsupervised Clustering of Time Series Signals Using Neuromorphic Energy-Efficient Temporal Neural Networks. - Shreyas Chaudhari; Harideep Nair; José M. F. Moura; John Paul Shen (ICASSP, 2021)

A Microarchitecture Implementation Framework for Online Learning with Temporal Neural Networks. - Harideep Nair; John Paul Shen; James E. Smith 001 (ISVLSI, 2021)

TNN7: A Custom Macro Suite for Implementing Highly Optimized Designs of Neuromorphic TNNs. - Harideep Nair; Prabhu Vellaisamy; Santha Bhasuthkar; John Paul Shen (ISVLSI, 2022)

SemNet: Learning semantic attributes for human activity recognition with deep belief networks. - Shanmuga Venkatachalam; Harideep Nair; Ming Zeng 009; Cathy Tan; Ole J. Mengshoel; John Paul Shen (Frontiers Big Data, 2022)

tuGEMM: Area-Power-Efficient Temporal Unary GEMM Architecture for Low-Precision Edge AI. - Harideep Nair; Prabhu Vellaisamy; Albert Chen 002; Joseph Finn; Anna Li; Manav Trivedi; John Paul Shen (ISCAS, 2023)

tubGEMM: Energy-Efficient and Sparsity-Effective Temporal-Unary-Binary Based Matrix Multiply Unit. - Prabhu Vellaisamy; Harideep Nair; Joseph Finn; Manav Trivedi; Albert Chen 002; Anna Li; Tsung-Han Lin; Perry H. Wang; Ronald Shawn Blanton; John Paul Shen (ISVLSI, 2023)

TNN-CIM: An In-SRAM CMOS Implementation of TNN-Based Synaptic Arrays with STDP Learning. - Harideep Nair; David Barajas-Jasso; Quinn Jacobson; John Paul Shen (AICAS, 2024)

Realtime Person Identification via Gait Analysis Using IMU Sensors on Edge Devices. - Shanmuga Venkatachalam; Harideep Nair; Prabhu Vellaisamy; Yongqi Zhou; Ziad Youssfi; John Paul Shen (ICONS, 2024)

Exploration of Unary Arithmetic-Based Matrix Multiply Units for Low Precision DL Accelerators. - Prabhu Vellaisamy; Harideep Nair; Di Wu; R. D. Shawn Blanton; John Paul Shen (ISVLSI, 2024)

NeRTCAM: CAM-Based CMOS Implementation of Reference Frames for Neuromorphic Processors. - Harideep Nair; William Leyman; Agastya Sampath; Quinn Jacobson; John Paul Shen (NICE, 2024)

Commercial Evaluation of Zero-Skipping MAC Design for Bit Sparsity Exploitation in DL Inference. - Harideep Nair; Prabhu Vellaisamy; Tsung-Han Lin; Perry H. Wang; Ronald Shawn Blanton; John Paul Shen (VLSI-SoC, 2024)

OzMAC: An Energy-Efficient Sparsity-Exploiting Multiply-Accumulate-Unit Design for DL Inference. - Harideep Nair; Prabhu Vellaisamy; Tsung-Han Lin; Perry H. Wang; Ronald Shawn Blanton; John Paul Shen (CoRR, 2024)

Realtime Person Identification via Gait Analysis. - Shanmuga Venkatachalam; Harideep Nair; Prabhu Vellaisamy; Yongqi Zhou; Ziad Youssfi; John Paul Shen (CoRR, 2024)

Corrigendum: SemNet: Learning semantic attributes for human activity recognition with deep belief networks. - Shanmuga Venkatachalam; Harideep Nair; Ming Zeng 009; Cathy Tan; Ole J. Mengshoel; John Paul Shen (Frontiers Big Data, 2024)

TNNGen: Automated Design of Neuromorphic Sensory Processing Units for Time-Series Clustering. - Prabhu Vellaisamy; Harideep Nair; Vamsikrishna Ratnakaram; Dhruv Gupta; John Paul Shen (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Tempus Core: Area-Power Efficient Temporal-Unary Convolution Core for Low-Precision Edge DLAs. - Prabhu Vellaisamy; Harideep Nair; Thomas Kang; Yichen Ni; Haoyang Fan; Bin Qi; Jeff Chen; R. D. Shawn Blanton; John Paul Shen (DATE, 2025)