Efficient fault tolerant cache memory design. - Haridimos T. Vergos; Dimitris Nikolos (Microprocess. Microprogramming, 1995)

Yield - Performance Tradeoffs for VLSI Processors with Partially Good Two-Level On-Chip Caches. - Dimitris Nikolos; Haridimos T. Vergos; Antonis Vazaios; Spyros Voulgaris (DFT, 1996)

Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers. - G. Sidiropoulos; Haridimos T. Vergos; Dimitris Nikolos (Asian Test Symposium, 1999)

Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks. - Dimitris Nikolos; Haridimos T. Vergos; Th. Haniotakis; Y. Tsiatouhas (DATE, 1999)

Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. - Xrysovalantis Kavousianos; Dimitris Bakalis; Haridimos T. Vergos; Dimitris Nikolos; George Alexiou (DFT, 1999)

Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks. - Maciej Bellos; Dimitris Nikolos; Haridimos T. Vergos (EDCC, 1999)

On Path Delay Fault Testing of Multiplexer - Based Shifters. - Haridimos T. Vergos; Dimitris Nikolos; Y. Tsiatouhas; Th. Haniotakis; Michael Nicolaidis (Great Lakes Symposium on VLSI, 1999)

Path delay fault testing of Benes multistage interconnection networks. - Haridimos T. Vergos; Maciej Bellos; Dimitris Nikolos (ICECS, 1999)

Design and Analysis of On-Chip CPU Pipelined Caches. - C. Ninos; Haridimos T. Vergos; Dimitris Nikolos (VLSI, 1999)

On the Yield of VLSI Processors with On-Chip CPU Cache. - Dimitris Nikolos; Haridimos T. Vergos (IEEE Trans. Computers, 1999)

Modified Booth 1's complement and modulo 2n-1 multipliers. - Costas Efstathiou; Haridimos T. Vergos (ICECS, 2000)

Low Power BIST for Wallace Tree-Based Fast Multipliers. - Dimitris Bakalis; Dimitris Nikolos; George Alexiou; Emmanouil Kalligeros; Haridimos T. Vergos (ISQED, 2000)

High-Speed Parallel-Prefix Modulo 2n-1 Adders. - Lampros Kalampoukas; Dimitris Nikolos; Costas Efstathiou; Haridimos T. Vergos; John Kalamatianos (IEEE Trans. Computers, 2000)

High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands. - Haridimos T. Vergos; Dimitris Nikolos; Costas Efstathiou (IEEE Symposium on Computer Arithmetic, 2001)

On the design of modulo 2n±1 adders. - Costas Efstathiou; Haridimos T. Vergos; Dimitris Nikolos (ICECS, 2001)

On Accumulator-Based Bit-Serial Test Response Compaction Schemes. - Dimitris Bakalis; Dimitris Nikolos; Haridimos T. Vergos; Xrysovalantis Kavousianos (ISQED, 2001)

A Formal Test Set for RNS Adders and an Efficient Low Power BIST Scheme. - Haridimos T. Vergos; Dimitris Nikolos; Maciej Bellos; Costas Efstathiou (LATW, 2001)

Low Power Built-In Self-Test Schemes for Array and Booth Multipliers. - Dimitris Bakalis; Xrysovalantis Kavousianos; Haridimos T. Vergos; Dimitris Nikolos; G. Ph. Alexiou (VLSI Design, 2001)

Ling adders in CMOS standard cell technologies. - Costas Efstathiou; Haridimos T. Vergos; Dimitris Nikolos (ICECS, 2002)

On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation. - Dimitris Bakalis; Emmanouil Kalligeros; Dimitris Nikolos; Haridimos T. Vergos; George Alexiou (J. Syst. Archit., 2002)

Diminished-One Modulo 2n+1 Adder Design. - Haridimos T. Vergos; Costas Efstathiou; Dimitris Nikolos (IEEE Trans. Computers, 2002)

A Family of Parallel-Pre.x Modulo 2n - 1 Adders. - Giorgos Dimitrakopoulos; Haridimos T. Vergos; Dimitris Nikolos; Costas Efstathiou (ASAP, 2003)

Efficient modulo 2n+1 tree multipliers for diminished-1 operands. - Costas Efstathiou; Haridimos T. Vergos; Giorgos Dimitrakopoulos; Dimitris Nikolos (ICECS, 2003)

An Efficient BIST scheme for High-Speed Adders. - Dimitris G. Nikolos; Dimitris Nikolos; Haridimos T. Vergos; Costas Efstathiou (IOLTS, 2003)

A systematic methodology for designing area-time efficient parallel-prefix modulo 2n - 1 adders. - Giorgos Dimitrakopoulos; Haridimos T. Vergos; Dimitris Nikolos; Costas Efstathiou (ISCAS (5), 2003)

Efficient BIST schemes for RNS datapaths. - Dimitris G. Nikolos; Dimitris Nikolos; Haridimos T. Vergos; Costas Efstathiou (ISCAS (5), 2003)

Modulo 2n±1 Adder Design Using Select-Prefix Blocks. - Costas Efstathiou; Haridimos T. Vergos; Dimitris Nikolos (IEEE Trans. Computers, 2003)

Deterministic BIST for RNS Adders. - Haridimos T. Vergos; Dimitris Nikolos; Maciej Bellos; Costas Efstathiou (IEEE Trans. Computers, 2003)

Diminished-1 Modulo 2n + 1 Squarer Design. - Haridimos T. Vergos; Costas Efstathiou (DSD, 2004)

Modified Booth Modulo 2n-1 Multipliers. - Costas Efstathiou; Haridimos T. Vergos; Dimitris Nikolos (IEEE Trans. Computers, 2004)

Fast Parallel-Prefix Modulo 2^n+1 Adders. - Costas Efstathiou; Haridimos T. Vergos; Dimitris Nikolos (IEEE Trans. Computers, 2004)

Modulo 2n - 1 multiplication/sum-of-squares units. - D. Adamidis; Haridimos T. Vergos (ECCTD, 2005)

New architectures for modulo 2N - 1 adders. - Giorgos Dimitrakopoulos; Dimitris G. Nikolos; Haridimos T. Vergos; Dimitris Nikolos; Costas Efstathiou (ICECS, 2005)

KoVer: A Sophisticated Residue Arithmetic Core Generator. - Nikolaos Kostaras; Haridimos T. Vergos (IEEE International Workshop on Rapid System Prototyping, 2005)

On the Design of Efficient Modular Adders. - Haridimos T. Vergos; Costas Efstathiou (J. Circuits Syst. Comput., 2005)

Efficient Diminished-1 Modulo 2^n+1 Multipliers. - Costas Efstathiou; Haridimos T. Vergos; Giorgos Dimitrakopoulos; Dimitris Nikolos (IEEE Trans. Computers, 2005)

Novel Modulo 2n + 1 Multipliers. - Haridimos T. Vergos; Costas Efstathiou (DSD, 2006)

A core generator for arithmetic cores and testing structures with a network interface. - Dimitris Bakalis; Kostas Adaos; Dimitrios Lymperopoulos; Maciej Bellos; Haridimos T. Vergos; George Alexiou; Dimitris Nikolos (J. Syst. Archit., 2006)

An Efficient BIST Scheme for Non-Restoring Array Dividers. - Haridimos T. Vergos (DSD, 2007)

RNS multiplication/sum-of-squares units. - D. Adamidis; Haridimos T. Vergos (IET Comput. Digit. Tech., 2007)

Design of efficient modulo 2n+1 multipliers. - Haridimos T. Vergos; Costas Efstathiou (IET Comput. Digit. Tech., 2007)

On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components. - Haridimos T. Vergos; Dimitris Bakalis (DSD, 2008)

Efficient modulo 2n + 1 multi-operand adders. - Haridimos T. Vergos; Dimitris Bakalis; Costas Efstathiou (ICECS, 2008)

A Unifying Approach for Weighted and Diminished-1 Modulo 2n+1 Addition. - Haridimos T. Vergos; Costas Efstathiou (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Efficient architectures for modulo 2n-1 squares. - Anastasia Spyrou; Dimitris Bakalis; Haridimos T. Vergos (DPS, 2009)

Novel modulo 2n+1 subtractors. - Evangelos Vassalos; Dimitris Bakalis; Haridimos T. Vergos (DPS, 2009)

Efficient modulo 2n+1 adder architectures. - Haridimos T. Vergos; Costas Efstathiou (Integr., 2009)

Area-Efficient Multi-moduli Squarers for RNS. - Dimitris Bakalis; Haridimos T. Vergos (DSD, 2010)

SUT-RNS Forward and Reverse Converters. - Evangelos Vassalos; Dimitris Bakalis; Haridimos T. Vergos (ISVLSI (Selected papers), 2010)

A Family of Area-Time Efficient Modulo 2n+1 Adders. - Haridimos T. Vergos (ISVLSI, 2010)

Fast modulo 2n+1 multi-operand adders and residue generators. - Haridimos T. Vergos; Dimitris Bakalis; Costas Efstathiou (Integr., 2010)

On Implementing Efficient Modulo 2n + 1 Arithmetic Components. - Haridimos T. Vergos; Dimitris Bakalis (J. Circuits Syst. Comput., 2010)

Modulo 2^n+1 Arithmetic Units with Embedded Diminished-to-Normal Conversion. - Evangelos Vassalos; Dimitris Bakalis; Haridimos T. Vergos (DSD, 2011)

On the use of double-LSB and signed-LSB encodings for RNS. - Evangelos Vassalos; Dimitris Bakalis; Haridimos T. Vergos (DSP, 2011)

On the Design of Modulo 2n±1 Subtractors and Adders/Subtractors. - Evangelos Vassalos; Dimitris Bakalis; Haridimos T. Vergos (Circuits Syst. Signal Process., 2011)

Efficient modulo 2n±1 squarers. - Dimitris Bakalis; Haridimos T. Vergos; Anastasia Spyrou (Integr., 2011)

SUT-RNS Residue-to-Binary Converters Design. - Evangelos Vassalos; Dimitris Bakalis; Haridimos T. Vergos (DSD, 2012)

Area-time efficient end-around inverted carry adders. - Haridimos T. Vergos (Integr., 2012)

Area-time efficient multi-modulus adders and their applications. - Haridimos T. Vergos; Dimitris Bakalis (Microprocess. Microsystems, 2012)

On Modulo 2^n+1 Adder Design. - Haridimos T. Vergos; Giorgos Dimitrakopoulos (IEEE Trans. Computers, 2012)

Reverse converters for RNSs with diminished-one encoded channels. - Evangelos Vassalos; Dimitris Bakalis; Haridimos T. Vergos (EUROCON, 2013)

RNS assisted image filtering and edge detection. - Evangelos Vassalos; Dimitris Bakalis; Haridimos T. Vergos (DSP, 2013)

Fast parallel-prefix Ling-carry adders in QCA nanotechnology. - Alexios Thanos; Haridimos T. Vergos (ICECS, 2013)

Easily verified IP watermarking. - Anastasios N. Bikos; Haridimos T. Vergos (DTIS, 2014)

Lookahead Architectures for Hamming Distance and Fixed-Threshold Hamming Weight Comparators. - Haridimos T. Vergos; Dimitris Bakalis; A. Anastasiou (Circuits Syst. Signal Process., 2015)

Extending the viability of power signature - Based IP watermarking in the SoC era. - George Blanas; Haridimos T. Vergos (ICECS, 2016)