Clock and data recovery module in 90nm for 10Gbps serial link with -18dB channel attenuation. - Harijot Singh Bindra; Shouri Chatterjee; Kaushik Saha; Taranjit Kukal (ISCAS, 2013)

Range pre-selection sampling technique to reduce input drive energy for SAR ADCs. - Harijot Singh Bindra; Joeri Lechevallier; Anne-Johan Annema; Simon M. Louwsma; Ed van Tuijl; Bram Nauta (A-SSCC, 2017)

An energy reduced sampling technique applied to a 10b 1MS/s SAR ADC. - Harijot Singh Bindra; Anne-Johan Annema; Simon M. Louwsma; Ed J. M. van Tuijl; Bram Nauta (ESSCIRC, 2017)

A 30fJ/comparison dynamic bias comparator. - Harijot Singh Bindra; Chris E. Lokin; Anne-Johan Annema; Bram Nauta (ESSCIRC, 2017)

A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise. - Harijot Singh Bindra; Chris E. Lokin; Daniël Schinkel; Anne-Johan Annema; Bram Nauta (IEEE J. Solid State Circuits, 2018)

A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply. - Harijot Singh Bindra; Anne-Johan Annema; Gerard Wienk; Bram Nauta; Simon M. Louwsma (CICC, 2019)

A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator. - Harijot Singh Bindra; Anne-Johan Annema; Simon M. Louwsma; Bram Nauta (VLSI Circuits, 2019)

Energy Efficient Startup of Crystal Oscillators Using Stepwise Charging. - Joeri Lechevallier; Harijot Singh Bindra; Ronan A. R. van der Zee; Bram Nauta (IEEE J. Solid State Circuits, 2021)

A 174μVRMS Input Noise, 1 G8/s Comparator in 22nm FDSOI with a Dynamic-Bias Preamplifier Using Tail Charge Pump and Capacitive Neutralization Across the Latch. - Harijot Singh Bindra; Jeroen Ponte; Bram Nauta (ISSCC, 2022)

Reconstructing Aliased Frequency Spectra by Using Multiple Sample Rates. - Maikel Huiskamp; Mark S. Oude Alink; Bram Nauta; Anne-Johan Annema; Harijot Singh Bindra (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 14-Bit Oversampled SAR ADC With Mismatch Error Shaping and Analog Range Compensation. - Yuting Shen; Hanyue Li; Harijot Singh Bindra; Eugenio Cantatore; Pieter Harpe (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Time Modulated Array and Time Variant Filter Techniques to Reduce Receiver Hardware Complexity and Power Consumption. - Viswesh Kendae Ramkumar; Harijot Singh Bindra; Eric A. M. Klumperink; Basem Abdelaziz Abdelmagid; H. Wang (EuCNC/6G Summit, 2025)

A 12.8GS/s Sub-Sampling ADC Front-End With 38GHz Input Bandwidth and >39dB SNDR for 1 to 32GHz in 22nm FDSOI. - Josef Heel; Harijot Singh Bindra; Simon M. Louwsma; Alessandro Dezzani; Bram Nauta (ISSCC, 2025)

A Programmable Filtering and Frequency Translation by Aliasing IF Receiver With Alias and Harmonic Rejection. - Viswesh Kendae Ramkumar; Maikel Huiskamp; Harijot Singh Bindra; Eric A. M. Klumperink; Bram Nauta (IEEE J. Solid State Circuits, 2025)