A hybrid cmos/nano fpga architecture built fromprogrammable majority logic arrays. - Harika Manem; Peter C. Paliwoda; Garrett S. Rose (ACM Great Lakes Symposium on VLSI, 2008)

The effects of logic partitioning in a majority logic based CMOS-NANO FPGA. - Harika Manem; Garrett S. Rose (ACM Great Lakes Symposium on VLSI, 2009)

Inversion schemes for sublithographic programmable logic arrays. - Benjamin Gojman; Harika Manem; Garrett S. Rose; André DeHon (IET Comput. Digit. Tech., 2009)

Design considerations for variation tolerant multilevel CMOS/Nano memristor memory. - Harika Manem; Garrett S. Rose; Xiaoli He; Wei Wang 003 (ACM Great Lakes Symposium on VLSI, 2010)

Memristor based programmable threshold logic array. - Jeyavijayan Rajendran; Harika Manem; Ramesh Karri; Garrett S. Rose (NANOARCH, 2010)

A read-monitored write circuit for 1T1M multi-level memristor memories. - Harika Manem; Garrett S. Rose (ISCAS, 2011)

An Approach to Tolerate Process Related Variations in Memristor-Based Applications. - Jeyavijayan Rajendran; Harika Manem; Ramesh Karri; Garrett S. Rose (VLSI Design, 2011)

Design Considerations for Multilevel CMOS/Nano Memristive Memory. - Harika Manem; Jeyavijayan Rajendran; Garrett S. Rose (ACM J. Emerg. Technol. Comput. Syst., 2012)

Leveraging Memristive Systems in the Construction of Digital Logic Circuits. - Garrett S. Rose; Jeyavijayan Rajendran; Harika Manem; Ramesh Karri; Robinson E. Pino (Proc. IEEE, 2012)

An Energy-Efficient Memristive Threshold Logic Circuit. - Jeyavijayan Rajendran; Harika Manem; Ramesh Karri; Garrett S. Rose (IEEE Trans. Computers, 2012)

Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array. - Harika Manem; Jeyavijayan Rajendran; Garrett S. Rose (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

An extendable multi-purpose 3D neuromorphic fabric using nanoscale memristors. - Harika Manem; Karsten Beckmann; Min Xu; Robert Carroll; Robert E. Geer; Nathaniel C. Cady (CISDA, 2015)

Techniques for Improved Reliability in Memristive Crossbar PUF Circuits. - Mesbah Uddin; Md. Badruddoja Majumder; Garrett S. Rose; Karsten Beckmann; Harika Manem; Zahiruddin Alamgir; Nathaniel C. Cady (ISVLSI, 2016)

Performance Enhancement of a Time-Delay PUF Design by Utilizing Integrated Nanoscale ReRAM Devices. - Karsten Beckmann; Harika Manem; Nathaniel C. Cady (IEEE Trans. Emerg. Top. Comput., 2017)

Design Considerations for Memristive Crossbar Physical Unclonable Functions. - Mesbah Uddin; Md. Badruddoja Majumder; Karsten Beckmann; Harika Manem; Zahiruddin Alamgir; Nathaniel C. Cady; Garrett S. Rose (ACM J. Emerg. Technol. Comput. Syst., 2018)