Asynchronous CLS for Zero Crossing based Circuits. - Hariprasath Venkatram; Benjamin P. Hershberg; Un-Ku Moon (ICECS, 2010)

A 10b Ternary SAR ADC with decision time quantization based redundancy. - Jon Guerber; Manideep Gande; Hariprasath Venkatram; Allen Waters; Un-Ku Moon (A-SSCC, 2011)

Enhanced SAR ADC energy efficiency from the early reset merged capacitor switching algorithm. - Jon Guerber; Hariprasath Venkatram; Taehwan Oh; Un-Ku Moon (ISCAS, 2012)

Correlated jitter sampling for jitter cancellation in pipelined TDC. - Taehwan Oh; Hariprasath Venkatram; Jon Guerber; Un-Ku Moon (ISCAS, 2012)

Class A+ amplifier with controlled positive feedback for discrete-time signal processing circuits. - Hariprasath Venkatram; Taehwan Oh; Jon Guerber; Un-Ku Moon (ISCAS, 2012)

A 10-b Ternary SAR ADC With Quantization Time Information Utilization. - Jon Guerber; Hariprasath Venkatram; Manideep Gande; Allen Waters; Un-Ku Moon (IEEE J. Solid State Circuits, 2012)

Blind background calibration of harmonic distortion based on selective sampling. - Manideep Gande; Ho-Young Lee; Hariprasath Venkatram; Jon Guerber; Un-Ku Moon (CICC, 2013)

Parallel gain enhancement technique for switched-capacitor circuits. - Hariprasath Venkatram; Benjamin P. Hershberg; Taehwan Oh; Manideep Gande; Kazuki Sobue; Koichi Hamashita; Un-Ku Moon (CICC, 2013)

A 62mW stereo class-G headphone driver with 108dB dynamic range and 600µA/channel quiescent current. - Jianlong Chen; Sasi Kumar Arunachalam; Todd Brooks; Iuri Mehr; Felix Cheung; Hariprasath Venkatram (ISSCC, 2013)

Detection and Correction Methods for Single Event Effects in Analog to Digital Converters. - Hariprasath Venkatram; Jon Guerber; Manideep Gande; Un-Ku Moon (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s pipelined ADC using hybrid dynamic amplifier. - Hariprasath Venkatram; Taehwan Oh; Kazuki Sobue; Koichi Hamashita; Un-Ku Moon (VLSIC, 2014)

Blind Calibration Algorithm for Nonlinearity Correction Based on Selective Sampling. - Manideep Gande; Hariprasath Venkatram; Ho-Young Lee; Jon Guerber; Un-Ku Moon (IEEE J. Solid State Circuits, 2014)

A Time-Based Pipelined ADC Using Both Voltage and Time Domain Information. - Taehwan Oh; Hariprasath Venkatram; Un-Ku Moon (IEEE J. Solid State Circuits, 2014)

Bit-error-rate analysis and mixed signal triple modular redundancy methods for data converters. - Jason Muhlestein; Hariprasath Venkatram; Jon Guerber; Allen Waters; Un-Ku Moon (ICECS, 2015)

A Continuous-Time ΔΣ ADC Utilizing Time Information for Two Cycles of Excess Loop Delay Compensation. - Yue Hu; Hariprasath Venkatram; Nima Maghari; Un-Ku Moon (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A Digital-Intensive 2-to-9.2 GB/S/Pin Memory Controller I/O with Fast-Response LDO in 10NM CMOS. - Rajesh Inti; Mozhgan Mansuri; Joe Kennedy 001; Hariprasath Venkatram; Chun-Ming Hsu; Aaron Martin; James E. Jaussi; Bryan Casper (VLSI Circuits, 2018)