Haris Volos

Orcid: 0000-0002-3777-0012

Affiliations:
  • University of Cyprus, Nicosia, Cyprus
  • Google, USA (former)
  • Hewlett Packard Labs, Palo Alto, CA, USA (former)
  • University of Wisconsin - Madison, Madison, WI, USA (former)


According to our database1, Haris Volos authored at least 23 papers between 2007 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

Online presence:

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Bibliography

2022
AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

AgilePkgC: An Agile System Idle State Architecture for Energy Proportional Datacenter Servers.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

2021
Unified Holistic Memory Management Supporting Multiple Big Data Processing Frameworks over Hybrid Memories.
ACM Trans. Comput. Syst., 2021

MODC: Resilience for disaggregated memory architectures using task-based programming.
CoRR, 2021

The Case for Replication-Aware Memory-Error Protection in Disaggregated Memory.
IEEE Comput. Archit. Lett., 2021

2019
Panthera: holistic memory management for big data processing over hybrid memories.
Proceedings of the 40th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2019

2018
Memory-Oriented Distributed Computing at Rack Scale.
Proceedings of the ACM Symposium on Cloud Computing, 2018

2017
Sparkle: optimizing spark for large memory machines and analytics.
Proceedings of the 2017 Symposium on Cloud Computing, SoCC 2017, Santa Clara, CA, USA, 2017

An Analysis of Persistent Memory Use with WHISPER.
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

2016
Interconnect Emulator for Aiding Performance Analysis of Distributed Memory Applications.
Proceedings of the 7th ACM/SPEC International Conference on Performance Engineering, 2016

2015
A Framework for Emulating Non-Volatile Memory Systemswith Different Performance Characteristics.
Proceedings of the 6th ACM/SPEC International Conference on Performance Engineering, Austin, TX, USA, January 31, 2015

Quartz: A Lightweight Performance Emulator for Persistent Memory Software.
Proceedings of the 16th Annual Middleware Conference, Vancouver, BC, Canada, December 07, 2015

InterSense: Interconnect Performance Emulator for Future Scale-out Distributed Memory Applications.
Proceedings of the 23rd IEEE International Symposium on Modeling, 2015

2014
In-Memory Performance for Big Data.
Proc. VLDB Endow., 2014

Aerie: flexible file-system interfaces to storage-class memory.
Proceedings of the Ninth Eurosys Conference 2014, 2014

2013
Storage-class memory needs flexible interfaces.
Proceedings of the Asia-Pacific Workshop on Systems, 2013

2012
Applying transactional memory to concurrency bugs.
Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems, 2012

2011
Mnemosyne: lightweight persistent memory.
Proceedings of the 16th International Conference on Architectural Support for Programming Languages and Operating Systems, 2011

2009
xCalls: safe I/O in memory transactions.
Proceedings of the 2009 EuroSys Conference, Nuremberg, Germany, April 1-3, 2009, 2009

NePaLTM: Design and Implementation of Nested Parallelism for Transactional Memory Systems.
Proceedings of the ECOOP 2009, 2009

2008
Performance Pathologies in Hardware Transactional Memory.
IEEE Micro, 2008

2007
LogTM-SE: Decoupling Hardware Transactional Memory from Caches.
Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007

A Case for Deconstructing Hardware Transactional Memory Systems.
Proceedings of the Programming Models for Ubiquitous Parallelism, 02.09. - 07.09.2007, 2007


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