A Case for Deconstructing Hardware Transactional Memory Systems. - Mark D. Hill; Derek Hower; Kevin E. Moore; Michael M. Swift; Haris Volos 001; David A. Wood 001 (Programming Models for Ubiquitous Parallelism, 2007)

LogTM-SE: Decoupling Hardware Transactional Memory from Caches. - Luke Yen; Jayaram Bobba; Michael R. Marty; Kevin E. Moore; Haris Volos 001; Mark D. Hill; Michael M. Swift; David A. Wood 001 (HPCA, 2007)

Performance Pathologies in Hardware Transactional Memory. - Jayaram Bobba; Kevin E. Moore; Haris Volos 001; Luke Yen; Mark D. Hill; Michael M. Swift; David A. Wood 001 (IEEE Micro, 2008)

NePaLTM: Design and Implementation of Nested Parallelism for Transactional Memory Systems. - Haris Volos 001; Adam Welc; Ali-Reza Adl-Tabatabai; Tatiana Shpeisman; Xinmin Tian; Ravi Narayanaswamy (ECOOP, 2009)

xCalls: safe I/O in memory transactions. - Haris Volos 001; Andres Jaan Tack; Neelam Goyal; Michael M. Swift; Adam Welc (EuroSys, 2009)

Mnemosyne: lightweight persistent memory. - Haris Volos 001; Andres Jaan Tack; Michael M. Swift (ASPLOS, 2011)

Applying transactional memory to concurrency bugs. - Haris Volos 001; Andres Jaan Tack; Michael M. Swift; Shan Lu 001 (ASPLOS, 2012)

Storage-class memory needs flexible interfaces. - Haris Volos 001; Sankaralingam Panneerselvam; Sanketh Nalli; Michael M. Swift (APSys, 2013)

Aerie: flexible file-system interfaces to storage-class memory. - Haris Volos 001; Sanketh Nalli; Sankaralingam Panneerselvam; Venkatanathan Varadarajan; Prashant Saxena; Michael M. Swift (EuroSys, 2014)

In-Memory Performance for Big Data. - Goetz Graefe; Haris Volos 001; Hideaki Kimura 001; Harumi A. Kuno; Joseph A. Tucek; Mark Lillibridge; Alistair C. Veitch (Proc. VLDB Endow., 2014)

InterSense: Interconnect Performance Emulator for Future Scale-out Distributed Memory Applications. - Qi Wang; Ludmila Cherkasova; Jun Li 008; Haris Volos 001 (MASCOTS, 2015)

Quartz: A Lightweight Performance Emulator for Persistent Memory Software. - Haris Volos 001; Guilherme Magalhaes; Ludmila Cherkasova; Jun Li 008 (Middleware, 2015)

A Framework for Emulating Non-Volatile Memory Systemswith Different Performance Characteristics. - Dipanjan Sengupta; Qi Wang; Haris Volos 001; Ludmila Cherkasova; Jun Li 008; Guilherme Magalhaes; Karsten Schwan (ICPE, 2015)

Interconnect Emulator for Aiding Performance Analysis of Distributed Memory Applications. - Qi Wang; Ludmila Cherkasova; Jun Li 008; Haris Volos 001 (ICPE, 2016)

An Analysis of Persistent Memory Use with WHISPER. - Sanketh Nalli; Swapnil Haria; Mark D. Hill; Michael M. Swift; Haris Volos 001; Kimberly Keeton (ASPLOS, 2017)

Sparkle: optimizing spark for large memory machines and analytics. - Mijung Kim; Jun Li 008; Haris Volos 001; Manish Marwah; Alexander Ulanov; Kimberly Keeton; Joseph A. Tucek; Lucy Cherkasova; Le Xu; Pradeep Fernando (SoCC, 2017)

Memory-Oriented Distributed Computing at Rack Scale. - Haris Volos 001; Kimberly Keeton; Yupu Zhang; Milind Chabbi; Se Kwon Lee; Mark Lillibridge; Yuvraj Patel; Wei Zhang 052 (SoCC, 2018)

Panthera: holistic memory management for big data processing over hybrid memories. - Chenxi Wang; Huimin Cui; Ting Cao; John N. Zigman; Haris Volos 001; Onur Mutlu; Fang Lv; Xiaobing Feng 002; Guoqing Harry Xu (PLDI, 2019)

The Case for Replication-Aware Memory-Error Protection in Disaggregated Memory. - Haris Volos 001 (IEEE Comput. Archit. Lett., 2021)

MODC: Resilience for disaggregated memory architectures using task-based programming. - Kimberly Keeton; Sharad Singhal; Haris Volos 001; Yupu Zhang; Ramesh Chandra Chaurasiya; Clarete Riana Crasta; Sherin T. George; Nagaraju K. N; Mashood Abdulla K; Kavitha Natarajan; Porno Shome; Sanish Suresh (CoRR, 2021)

Unified Holistic Memory Management Supporting Multiple Big Data Processing Frameworks over Hybrid Memories. - Lei Chen; Jiacheng Zhao; Chenxi Wang; Ting Cao; John N. Zigman; Haris Volos 001; Onur Mutlu; Fang Lv; Xiaobing Feng 002; Guoqing Harry Xu; Huimin Cui (ACM Trans. Comput. Syst., 2021)

AgilePkgC: An Agile System Idle State Architecture for Energy Proportional Datacenter Servers. - Georgia Antoniou; Haris Volos 001; Davide B. Bartolini; Tom Rollet; Yiannakis Sazeides; Jawad Haj-Yahya (MICRO, 2022)

AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications. - Jawad Haj-Yahya; Haris Volos 001; Davide B. Bartolini; Georgia Antoniou; Jeremie S. Kim; Zhe Wang 023; Kleovoulos Kalaitzidis; Tom Rollet; Zhirui Chen; Ye Geng; Onur Mutlu; Yiannakis Sazeides (MICRO, 2022)

Taming Performance Variability caused by Client-Side Hardware Configuration. - Georgia Antoniou; Haris Volos 001; Yiannakis Sazeides (IISWC, 2024)

Agile C-states: A Core C-state Architecture for Latency Critical Applications Optimizing both Transition and Cold-Start Latency. - Georgia Antoniou; Davide B. Bartolini; Haris Volos 001; Marios Kleanthous; Zhe Wang 023; Kleovoulos Kalaitzidis; Tom Rollet; Ziwei Li; Onur Mutlu; Yiannakis Sazeides; Jawad Haj-Yahya (ACM Trans. Archit. Code Optim., 2024)

Leveraging control-flow similarity to reduce branch predictor cold effects in microservices. - Haris Volos 001; Stylianos Vassiliou; Georgia Antoniou; Davide Basilio Bartolini; Yiannakis Sazeides (ISCA, 2025)

SAGA: A Surrogate Assisted Genetic Algorithm for Fast CPU Power Virus Generation. - Panteleimonas Chatzimiltis; Georgia Antoniou; Haris Volos 001; Yiannakis Sazeides (ISPASS, 2025)

Analyzing a Two-Tier Disaggregated Memory Protection Scheme Based on Memory Replication. - Haris Volos 001; Yiannakis Sazeides (CoRR, 2025)